-
公开(公告)号：US20200176039A1
公开(公告)日：2020-06-04
申请号：US16731948
申请日：2019-12-31
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.
-
282.发明授权公开(公告)号：US10672833B2
公开(公告)日：2020-06-02
申请号：US15660491
申请日：2017-07-26
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer
Abstract: A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.
-
公开(公告)号：US20200119273A1
公开(公告)日：2020-04-16
申请号：US16706358
申请日：2019-12-06
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
-
公开(公告)号：US10600481B2
公开(公告)日：2020-03-24
申请号：US16105874
申请日：2018-08-20
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Innocenzo Tortorelli , Andrea Redaelli , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.
-
公开(公告)号：US20200052035A1
公开(公告)日：2020-02-13
申请号：US16656824
申请日：2019-10-18
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Russell L. Meyer , Agostino Pirovano , Lorenzo Fratin
Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.
-
Patent Agency Ranking
公开(公告)号：US20200035917A1
公开(公告)日：2020-01-30
申请号：US16537119
申请日：2019-08-09
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Fabio Pellizzer
Abstract: A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar.
-
公开(公告)号：US10546632B2
公开(公告)日：2020-01-28
申请号：US15842496
申请日：2017-12-14
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
-
公开(公告)号：US20200013463A1
公开(公告)日：2020-01-09
申请号：US16518847
申请日：2019-07-22
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
-
公开(公告)号：US10483463B2
公开(公告)日：2019-11-19
申请号：US16121433
申请日：2018-09-04
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Giorgio Servalli , Carmela Cupeta , Fabio Pellizzer
Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.
-
公开(公告)号：US10446226B2
公开(公告)日：2019-10-15
申请号：US15231518
申请日：2016-08-08
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
-
-
-
-
-
-
-
-
-
Search Results
410
records
(took 0.026 seconds)
