Abstract:
An apparatus arranged to accept digital data as an input and to process the data according to one of either the Secure Hash Algorithm (SHA-1) or Message Digest (MD5) algorithm to produce a fixed length output word. The apparatus includes a plurality of rotational registers for storing data, one of the registers arranged to receive the input data, and data stores for initialization of some of the plurality of registers according to whether the SHA-1 or MD5 algorithm is used. The data stores include fixed data relating to SHA-1 and MD5 operation. Also included is a plurality of dedicated combinatorial logic circuits arranged to perform logic operations on data stored in selected ones of the plurality of registers.
Abstract:
A method of processing video data to detect field characteristics of the data, said data having a plurality of fields, including the steps of: comparing first and second fields, said first field being a successive field of said second field; comparing pixel values of respective sub-blocks of said first field and a third field, said second field being a successive field of said third field; determining whether said first field is an interlaced field or a progressive field with respect to a successive field of said first field based on said steps of comparing.
Abstract:
Two preferred embodiments provide slot synchronization of an initial cell search. Two Finite Impulse Response (FIR) filters are used to correlate the synchronization codes transmitted in the downlink (forward link). A sign bit is taken after the first FIR to significantly reduce the hardware requirements for the second FIR, and thus the whole system. The correlated results from the second FIR can be further processed using two different algorithms. The first adds a square operation to the correlated results whilst the second takes the magnitude before passing to the next stage. Regardless of which algorithm is adopted, the results are accumulated (I and Q), instead of averaged, and stored in a memory location for each successive correlation over the same location in different slots. The physical-layer processor (PLP) then reads the accumulated results from the memory location and searches for the peak position corresponding to the slot boundary.
Abstract:
A memory device includes a pre-charge transistor for connecting/disconnecting the input line of a global data line driver to a supply voltage line. To reduce the flow of current through the pre-charge transistor even in a stand-by state, the pre-charge transistor is turned on when, at a same time, an enabling signal of a page buffer is asserted, and a low voltage functioning mode is selected and the memory device is not in a stand-by state. Alternatively, the memory device may be in a stand-by state but the datum read from the memory is high. The pre-charge transistor is securely turned off in all other cases.
Abstract:
A method for enhancing the contrast of video pictures that includes the steps of receiving an input video signal; extracting a picture from said input video signal; determining an active window for said picture; calculating a histogram for luminance values of pixels in said active window of said picture; determining characteristics of said histogram; selecting one suitable mapping function from a plurality of mapping functions based on the determined characteristics of said histogram; and mapping the luminance value of each pixel in said picture in accordance with said selected mapping function.
Abstract:
In a process for enhancing contrast of an image having pixels in different brightness intensities, a histogram in discrete bins is generated. Each bin represents a pixel population of at least one pixel brightness intensity. A peak and a peak region of the histogram is then identified, wherein the peak region is a range of discrete bins around the peak. An average pixel population within the peak region is computed, and the pixel populations of the discrete bins within the peak region that exceeds the average pixel population are distributed. A transfer curve for mapping onto the image is then generated. The process can be used in an image processor for enhancing contrast of an image having pixel. Still further, a display having a receiver and a screen can include the foregoing image processor.
Abstract:
A system and method for adaptive rate control in audio processing is provided. The process could include receiving uncompressed audio data from an input and generating MDCT spectrum for each frame of the uncompressed audio data using a filterbank. The process could also include estimating masking thresholds for current frame to be encoded based on the MDCT spectrum. The masking thresholds reflect a bit budget for the current frame. The process could also include performing quantization of the current frame based on the masking thresholds. After the quantization of the current frame, the bit budget for next frame is updated for estimating the masking thresholds of the next frame. The process could also include encoding the quantized audio data.
Abstract:
An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.
Abstract:
A gain control circuit includes a light detector for generating an amount of current based on received light and a first switch for controlling the amount of current from the light detector delivered to a node. The gain control circuit also includes a charge storage element for providing an amount of capacitance to the node and a second switch for controlling the amount of capacitance provided to the node. The gain control circuit further includes an output interface for delivering an output signal based on the amount of current and the amount of capacitance at the node. The light detector may include multiple photodiodes, and the first switch may include a pair of NMOS switching transistors coupled to at least one photodiode. Also, the charge storage element may include multiple capacitors, and the second switch may include a PMOS transistor and an NMOS transistor coupled to each capacitor.
Abstract:
A method of transferring sets of video line data and macroblock data, includes the steps of determining a macroblock period and a video line period longer than the macroblock period, dividing each set of video line data to be transferred within the video line period into two or more portions according to the difference between the determined macroblock period and video line period, aligning a burst transfer of each of the portions of the divided set of video line data and each set of macroblock data to the macroblock period, and initiating the burst transfer of the sets of video line data and macroblock data at macroblock period intervals.