公开(公告)号：US07038720B2

公开(公告)日：2006-05-02

申请号：US10273407

申请日：2002-10-16

申请人： Charles Andrew Rogers ,  Richard Leigh Gower ,  Bhupendra Kumar Ahuja

发明人： Charles Andrew Rogers ,  Richard Leigh Gower ,  Bhupendra Kumar Ahuja

IPC分类号： H04N5/217

CPC分类号： H04N5/3655 ,  H04N1/48 ,  H04N5/3651 ,  H04N9/045

摘要： A method and apparatus for adjusting, on a pixel-by-pixel basis, the gain and offset in an AFE as the pixels are sequentially processed. Although the method can be used for any purpose, it is directed in particular to light source non-linearity, such as edge effects of a scanner. A unique clocking method clocks the gain and offset values into the register at a higher clock rate than the image sampling rate.

摘要翻译： 一种在逐像素的基础上随着像素被依次处理而调整AFE中的增益和偏移的方法和装置。 虽然该方法可以用于任何目的，但是其特别涉及光源非线性，例如扫描仪的边缘效应。 独特的时钟方法以比图像采样率更高的时钟速率将增益和偏移值计时到寄存器中。

公开(公告)号：US20060066359A1

公开(公告)日：2006-03-30

申请号：US10956357

申请日：2004-09-30

申请人： Vincent Tso ,  James Ho

发明人： Vincent Tso ,  James Ho

IPC分类号： H03K5/22

CPC分类号： H03K5/2481 ,  H03L7/10

摘要： To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter that converts the close-loop's voltage to a current and supplies a first voltage to the first and second transistors. The third and fourth currents are scaled replicas of a different current flowing through a current mirror of the voltage-to-current converter and that supplies a second voltage to the third and fourth transistors.

公开(公告)号：US20060065947A1

公开(公告)日：2006-03-30

申请号：US10326364

申请日：2002-12-20

申请人： Pekka Ojala

发明人： Pekka Ojala

IPC分类号： H01L29/00

CPC分类号： H01L21/761 ,  H01L27/08

摘要： A double well structure beneath an inductor to isolate it from the substrate. Contacts are provided for the deeper well and the substrate, to reverse bias the junction between the substrate and the deep well. In one embodiment, for a P-substrate, the deep well is an N-well, and the other well is a P-well. Both the N-well junction with the substrate, and the junction between the N-well and the P-well are reverse biased. This improves the quality factor of the inductor structure above the wells by reducing eddy currents. In one embodiment, the P-well is striped. The deeper N-well extends upward into the gaps between the stripes. The stripes will further reduce the amount of eddy current by adding a reverse biased sidewall junction to the eddy current path, further helping to increase the quality factor of the inductor.

摘要翻译： 在电感器下方的双阱结构，以将其与衬底隔离。 为较深的阱和衬底提供触点，以反向偏置衬底和深阱之间的结。 在一个实施方案中，对于P-底物，深井是N阱，另一个井是P阱。 与衬底的N阱结以及N阱和P阱之间的连接都是反向偏置的。 这可以通过减少涡流来改善井上电感器结构的品质因数。 在一个实施例中，P阱是条纹的。 较深的N阱向上延伸到条纹之间的间隙中。 通过将反向偏置的侧壁结加到涡流路径上，条纹将进一步减小涡流量，进一步有助于提高电感器的品质因数。

公开(公告)号：US06965606B2

公开(公告)日：2005-11-15

申请号：US09771172

申请日：2001-01-26

申请人： Sanjay Bhardwaj

发明人： Sanjay Bhardwaj

IPC分类号： H04J3/04 ,  H04J3/06 ,  H04J3/16 ,  H04L12/56 ,  G01R31/08

CPC分类号： H04J3/1617 ,  H04J3/047 ,  H04J3/0608 ,  H04J3/062 ,  H04L49/90

摘要： A scheme is described for distributing data operations on an irregular data stream over multiple stages of a data aligner to generate a regular data stream having continuous filled byte positions. In one particular embodiment, data alignment may involve the prediction of a rotation amount for unaligned data bytes. The rotation amount is predicted one clock cycle before actual rotation of data bytes based on the current contents of a buffer. The one cycle look ahead enables a large portion of calculations to be performed in a previous clock cycle and, thereby, may facilitate a high frequency design for a data aligner.

摘要翻译： 描述了用于在数据对准器的多个级上对不规则数据流分发数据操作以生成具有连续填充字节位置的规则数据流的方案。 在一个特定实施例中，数据对准可涉及对未对齐数据字节的旋转量的预测。 基于缓冲器的当前内容，在实际旋转数据字节之前的一个时钟周期预测旋转量。 前一个循环可以在以前的时钟周期中执行大部分计算，从而可以促进数据对准器的高频设计。

公开(公告)号：US06947999B1

公开(公告)日：2005-09-20

申请号：US09528089

申请日：2000-03-17

申请人： Glenn Wegner ,  Sun Man Lo

发明人： Glenn Wegner ,  Sun Man Lo

IPC分类号： H04B7/26 ,  G06F13/38 ,  G06F15/16

CPC分类号： G06F13/385

摘要： An improved UART which has a number of channels, with each channel having a set of channel configuration registers. Each channel configuration register includes an interrupt source register. The interrupt source register has a multi-bit interrupt source code which is used to indicate the source of the interrupt. This code is chosen to be compatible with prior UART devices. The device also includes a bus interface, and a plurality of device configuration registers accessible through the bus interface by a user. One of the device configuration registers is an interrupt register which provides a user accessible code to indicate the interrupt source. The code used for the interrupt source is a compressed version of the multiple bit code used in the channel configuration interrupt source register. This compression allows more channels to be represented in a single register, while also conveying the interrupt source information quickly to the user. Since the device interrupt register in the configuration registers is for access by the user, rather than internal access by UART drivers, there is no need for compatibility with the prior UART drivers.

摘要翻译： 具有多个通道的改进的UART，每个通道具有一组通道配置寄存器。 每个通道配置寄存器包括一个中断源寄存器。 中断源寄存器有一个多位中断源代码，用于指示中断源。 该代码被选择为与以前的UART器件兼容。 该设备还包括总线接口以及用户可通过总线接口访问的多个设备配置寄存器。 设备配置寄存器之一是一个中断寄存器，提供用户可访问的代码来指示中断源。 用于中断源的代码是通道配置中断源寄存器中使用的多位代码的压缩版本。 该压缩允许在单个寄存器中表示更多的通道，同时还向用户快速传递中断源信息。 由于配置寄存器中的器件中断寄存器是用户访问的，而不是UART驱动程序的内部访问，因此不需要与以前的UART驱动程序兼容。

公开(公告)号：US20040075748A1

公开(公告)日：2004-04-22

申请号：US10273407

申请日：2002-10-16

申请人： Exar Corporation

发明人： Charles Andrew Rogers ,  Richard Leigh Gower ,  Bhupendra Kumar Ahuja

IPC分类号： H04N005/228

CPC分类号： H04N5/3655 ,  H04N1/48 ,  H04N5/3651 ,  H04N9/045

摘要： A method and apparatus for adjusting, on a pixel-by-pixel basis, the gain and offset in an AFE as the pixels are sequentially processed. Although the method can be used for any purpose, it is directed in particular to light source non-linearity, such as edge effects of a scanner. A unique clocking method clocks the gain and offset values into the register at a higher clock rate than the image sampling rate.

摘要翻译： 一种在逐像素的基础上随着像素被依次处理而调整AFE中的增益和偏移的方法和装置。 虽然该方法可以用于任何目的，但是其特别涉及光源非线性，例如扫描仪的边缘效应。 独特的时钟方法以比图像采样率更高的时钟速率将增益和偏移值计时到寄存器中。

公开(公告)号：US20030190001A1

公开(公告)日：2003-10-09

申请号：US10118661

申请日：2002-04-08

申请人： Exar Corporation

发明人： Roubik Gregorian ,  Mir Bahram Ghaderi ,  James Ban Ho ,  Vincent Sing Tso

IPC分类号： H04L007/02

CPC分类号： H04L7/033 ,  H03L7/0891 ,  H03L7/091

摘要： A converting circuit which converts RZ data into intermeidate NRZ data. The intermediate NRZ data is then sampled to detect a phase of the intermediate NRZ data, which corresponds to the phase of the RZ data. In a preferred embodiment, the converting circuit is incorporated in a modified Hogge NRZ phase detector. A toggle flip-flop is placed in front of the Hogge phase detector. Since the toggle flip-flop is triggered by the leading edge of the RZ pulse, it essentially converts the RZ data into intermediate NRZ data. An exclusive-OR gate samples two different output stages of the Hogge NRZ phase detector, with the output stages being separated by an interim stage to provide a clock delay. The output of the exclusive-OR gate is an intermediate NRZ signal that corresponds to the input RZ data stream, which can then be sampled. The exclusive-OR gates inside the Hogge phase detector are used, as in the Hogge phase detector, to produce the up and down signals provided to a charge pump that is part of a PLL. The insertion of the toggle flip-flop allows these same exclusive-OR gates to perform the same function in the present invention.

摘要翻译： A转换电路，将RZ数据转换成中间NRZ数据。 然后对中间NRZ数据进行采样以检测对应于RZ数据的相位的中间NRZ数据的相位。 在优选实施例中，转换电路并入修改后的Hogge NRZ相位检测器中。 开关触发器位于Hogge相位检测器的前面。 由于切换触发器由RZ脉冲的前沿触发，所以它基本上将RZ数据转换成中间NRZ数据。 异或门对Hogge NRZ相位检测器的两个不同输出级进行采样，输出级由中间级分隔，以提供时钟延迟。 异或门的输出是对应于输入RZ数据流的中间NRZ信号，然后可以对其进行采样。 使用Hogge相位检测器内的异或门，如在霍格相位检测器中，产生提供给作为PLL一部分的电荷泵的上下信号。 切换触发器的插入允许这些相同的异或门在本发明中执行相同的功能。

公开(公告)号：US20020089801A1

公开(公告)日：2002-07-11

申请号：US09757987

申请日：2001-01-09

申请人： Exar Corporation

发明人： Robert Alan Brannen ,  Bahram Fotouhi

IPC分类号： H02H009/02

CPC分类号： H03F1/52

摘要： The present invention provides a short circuit power limiter circuit having a current sensor and a power limiter. The short circuit sensor sends a short circuit flag signal to the power limiter when the short circuit sensor detects a short circuit condition in a target circuit. The power limiter then reduces the power consumption of the target circuit. In a specific example, the power limiter toggles a particular portion of the target circuit on and off to reduce the circuit's average short circuit power consumption. This cycle is repeated as long as a short circuit condition exists.

摘要翻译： 本发明提供一种具有电流传感器和功率限制器的短路功率限制器电路。 当短路传感器检测到目标电路中的短路状况时，短路传感器向功率限制器发送短路标志信号。 功率限制器然后降低目标电路的功耗。 在具体示例中，功率限制器切换目标电路的特定部分的开和关，以减少电路的平均短路功耗。 只要存在短路状况，就重复该循环。

公开(公告)号：US5880623A

公开(公告)日：1999-03-09

申请号：US808822

申请日：1997-02-28

申请人： Roger Levinson

发明人： Roger Levinson

IPC分类号： G05F3/24 ,  G05F1/10

CPC分类号： G05F3/247

摘要： Method and circuitry for power control in integrated circuits using field effect transistor (FET) technology are disclosed. According to the present invention, for each circuit block that is biased by the power supply voltage a dedicated level shifter is inserted between the block and the power supply. In one embodiment, a switch is also coupled in parallel to the level shifter. The switch is closed when a low external power supply voltage is applied, and opened when a higher power supply voltage is applied. A second embodiment removes the switch and adds a bias generator that supplies a bias voltage to each level shifter.

摘要翻译： 公开了使用场效应晶体管（FET）技术的集成电路中功率控制的方法和电路。 根据本发明，对于由电源电压偏置的每个电路块，在块和电源之间插入专用电平移位器。 在一个实施例中，开关也与电平移位器并联耦合。 当施加低的外部电源电压时，开关闭合，并且当施加更高的电源电压时打开。 第二实施例去除开关并增加向每个电平移位器提供偏置电压的偏置发生器。

公开(公告)号：US5790393A

公开(公告)日：1998-08-04

申请号：US787416

申请日：1997-01-22

申请人： Bahram Fotouhi

发明人： Bahram Fotouhi

IPC分类号： H02M3/07 ,  H02M3/18

CPC分类号： H02M3/07

摘要： A circuit and method for generating a fractional multiple of a primary power supply voltage is disclosed. The circuit operates in two phases wherein during a first phase a first capacitor is charged to the primary power supply voltage Vdd, and during a second phase the voltage on the first capacitor is bootstrapped toward twice the power supply voltage. A second capacitor, however, is coupled in parallel to the first capacitor during the second phase to cause charge sharing. The circuit can thus generate a fractional voltage between Vdd and 2 Vdd without the need for any voltage regulator circuitry.

摘要翻译： 公开了一种用于产生主电源电压的分数倍的电路和方法。 电路工作在两个阶段，其中在第一阶段期间，第一电容器被充电到主电源电压Vdd，而在第二阶段期间，第一电容器上的电压被自举到电源电压的两倍。 然而，第二电容器在第二阶段期间并联耦合到第一电容器以引起电荷共享。 因此，电路可以在Vdd和2Vdd之间产生分数电压，而不需要任何电压调节器电路。