公开(公告)号：US08076752B2

公开(公告)日：2011-12-13

申请号：US11384961

申请日：2006-03-20

Applicant: Scott C. McLeod

Inventor： Scott C. McLeod

IPC: H01L29/00

CPC classification number: H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Capacitors configured in a switched-capacitor circuit on a semiconductor device may comprise very accurately matched, high capacitance density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer as a shield, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining. The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.

Abstract translation: 配置在半导体器件上的开关电容器电路中的电容器可以包括非常精确匹配的高电容密度的金属 - 金属电容器，使用顶板到底板的条纹电容来获得所需的电容值。 可以将多晶硅板插入底部金属层下面作为屏蔽，并且自举到每个电容器的顶板，以便最小化和/或消除寄生的顶板对衬底电容。 这可以释放用于形成额外的边缘电容的底部金属层，从而增加电容密度。 通过仅根据从顶板到底板的边缘电容形成每个电容，不使用平行板电容，这可以减少电容器失配。 也可以消除与衬底的寄生底板电容，仅剩余少量的自举多晶硅板的电容。 电容器可以通过将每个电容器的顶板耦合到开关电容器电路中包括的放大器的差分输入中的相应一个来自举。

公开(公告)号：US07991514B2

公开(公告)日：2011-08-02

申请号：US11557405

申请日：2006-11-07

Applicant: Alan D. Berenbaum ,  Richard E. Wahler ,  Eileen M. Marando

Inventor： Alan D. Berenbaum ,  Richard E. Wahler ,  Eileen M. Marando

IPC: G05D23/00

CPC classification number: G05D23/1917 ,  G06F1/206

Abstract: Temperature readings obtained within a computer system from the location of monitored circuit elements may be oversampled at least three times, and a median average of the three parameter readings rather than the arithmetic mean may be used for controlling a device, e.g. a fan, configured to regulate the environmental parameter, e.g. temperature, a the location of the monitored circuit elements. For example, when a CPU temperature reading is requested by the system comprising the CPU, a thermal monitoring system may acquire at least three consecutive temperature readings of the CPU, discard the highest temperature reading and the lowest temperature reading, and return the median reading to be used in controlling a fan configured to regulate temperature at the location of the CPU, resulting in more accurate temperature readings and more accurate fan control. In various implementations, more than three readings may be considered at a time, and running averages based on median values may be computed in a variety of ways to obtain a temperature control value to control the fan.

Abstract translation: 从受监控的电路元件的位置在计算机系统内获得的温度读数可以被过采样至少三次，并且三个参数读数而不是算术平均值的中值平均值可用于控制器件，例如， 风扇，被配置为调节环境参数，例如， 温度，监测电路元件的位置。 例如，当CPU系统要求CPU温度读数时，热监测系统可以获取至少三个CPU的连续温度读数，丢弃最高温度读数和最低温度读数，并将中位数读数返回到 用于控制配置为调节CPU位置温度的风扇，从而获得更准确的温度读数和更准确的风扇控制。 在各种实现中，可以一次考虑三个以上的读数，并且可以以多种方式计算基于中值的运行平均值，以获得控制风扇的温度控制值。

公开(公告)号：US07930576B2

公开(公告)日：2011-04-19

申请号：US11958601

申请日：2007-12-18

Applicant: Ian F. Harris ,  Drew J. Dutton

Inventor： Ian F. Harris ,  Drew J. Dutton

IPC: G06F1/26 ,  G06F15/177

CPC classification number: G06F13/16

Abstract: System and method for sharing a device, e.g., non-volatile memory, between a host processor and a microcontroller. In response to system state change to a first state wherein the microcontroller is assured safe access to the non-volatile memory (e.g., in response to power-on reset, system reset, sleep state, etc.), the microcontroller holds the system in the first state (e.g., system reset), and switches access to the non-volatile memory from the processor to the microcontroller. While the system is held in the first state, the microcontroller accesses the device (e.g., non-volatile memory), e.g., fetches program instructions/data from the non-volatile memory and loads the program instructions/data into a memory of the microcontroller. After the access, the microcontroller changes or allows change of the system state, e.g., switches access to the device, e.g., the non-volatile memory, from the microcontroller to the processor, and releases the system from the first state.

Abstract translation: 用于在主处理器和微控制器之间共享设备（例如，非易失性存储器）的系统和方法。 响应于系统状态改变到第一状态，其中微控制器被安全地访问非易失性存储器（例如，响应于上电复位，系统复位，睡眠状态等），微控制器将系统保持在 第一个状态（例如，系统复位），并切换从处理器到微控制器的非易失性存储器的访问。 当系统处于第一状态时，微控制器访问设备（例如，非易失性存储器），例如从非易失性存储器获取程序指令/数据，并将程序指令/数据加载到微控制器的存储器中 。 在访问之后，微控制器改变或允许系统状态的改变，例如，将从该微控制器的设备（例如，非易失性存储器）的访问切换到处理器，并将系统从第一状态释放。

公开(公告)号：US07890684B2

公开(公告)日：2011-02-15

申请号：US11469287

申请日：2006-08-31

Applicant: Alan D. Berenbaum ,  Jury Muchin

Inventor： Alan D. Berenbaum ,  Jury Muchin

IPC: G06F13/36 ,  G06F13/362 ,  G06F3/00 ,  G06F5/00 ,  G06F1/00 ,  G06F1/04 ,  G06F1/24 ,  G06F11/00

CPC classification number: G06F13/4031

Abstract: Return path clocking mechanism for a system including a master device connected to a plurality of slave devices via a bus. The master device may first generate a global clock. The master device may transmit data to one or more of the slave devices at a rate of one bit per clock cycle. One or more of the slave devices may transmit data to the master device at a rate of one bit per two consecutive clock cycles. The master device may sample the transmitted data on the second cycle of each two consecutive clock cycle period. Alternatively, the slave devices may transmit data to the master device at a rate of one bit per N consecutive clock cycles, where N≧2, and the master device may sample the transmitted data on the Nth cycle of each N consecutive clock cycle period.

Abstract translation: 用于包括经由总线连接到多个从设备的主设备的系统的返回路径计时机构。 主设备可以首先生成全局时钟。 主设备可以以每个时钟周期一位的速率向一个或多个从设备发送数据。 一个或多个从设备可以以每两个连续时钟周期的一比特的速率向主设备发送数据。 主设备可以在每两个连续的时钟周期周期的第二个周期对采样的数据进行采样。 或者，从设备可以以每N个连续时钟周期的一比特的速率向主设备发送数据，其中N≥2，并且主设备可以在每个N个连续时钟周期周期的第N个周期对所发送的数据进行采样。

公开(公告)号：US07809023B2

公开(公告)日：2010-10-05

申请号：US11961047

申请日：2007-12-20

Applicant: David J. Knapp ,  Patrick Heck

Inventor： David J. Knapp ,  Patrick Heck

IPC: H04J3/00

CPC classification number: H04J3/1682 ,  H04J3/0638 ,  H04J3/12

Abstract: A communication system, network interface, and communication port is provided for interconnecting a network of multimedia devices. The multimedia devices can send streaming and/or non-streaming data across the network. The network accommodates all such types of data and assigns data types to time slots or frame segments within each frame to ensure streaming data maintains its temporal relationship at the receiver consistent with the transmitter. A signaling byte is preferably used to keep track of an amount by which isochronous streaming data occupies a frame segment.

Abstract translation: 提供通信系统，网络接口和通信端口用于互连多媒体设备的网络。 多媒体设备可以通过网络发送流和/或非流数据。 网络容纳所有这些类型的数据，并将数据类型分配给每帧内的时隙或帧段，以确保流数据在接收机处保持其与发射机一致的时间关系。 信令字节优选地用于跟踪同步流数据占据帧段的量。

公开(公告)号：US07707437B2

公开(公告)日：2010-04-27

申请号：US11417855

申请日：2006-05-03

Applicant: Alan D. Berenbaum ,  Raphael Weiss

Inventor： Alan D. Berenbaum ,  Raphael Weiss

IPC: G06F1/00

CPC classification number: G06F13/42 ,  G06F1/3209

Abstract: A power state broadcast mechanism. A master device may broadcast a message through the use of a protocol to each of one or more slave devices to inform the slave devices of the power state of a computer system. The broadcast message may include a protocol header indicating the start of the broadcast transaction, a function type parameter indicating the type of broadcast transaction, and power state data indicating the power state of the computer system. Each of the slave devices may read the protocol header to detect the start of a broadcast transaction, and the function type parameter to determine the type of broadcast transaction. If the function type parameter indicates a power state broadcast transaction, each of the slave devices may read the power state data included in the broadcast message and determine whether to adjust the current power state of the slave device.

Abstract translation: 电力状态广播机制。 主设备可以通过使用协议向一个或多个从设备中的每一个广播消息，以向从设备通知计算机系统的电源状态。 广播消息可以包括指示广播事务的开始的协议头，指示广播事务的类型的功能类型参数，以及指示计算机系统的电源状态的电源状态数据。 每个从设备可以读取协议报头以检测广播事务的开始，以及功能类型参数来确定广播事务的类型。 如果功能类型参数指示功率状态广播事务，则每个从设备可以读取广播消息中包括的功率状态数据，并确定是否调整从设备的当前功率状态。

公开(公告)号：US07664214B2

公开(公告)日：2010-02-16

申请号：US10253681

申请日：2002-09-24

Applicant: David J. Knapp ,  Jason E. Lewis

Inventor： David J. Knapp ,  Jason E. Lewis

IPC: H04L7/00

CPC classification number: H04L7/04 ,  H03L7/06 ,  H03L7/07 ,  H04L7/0079 ,  H04L7/033 ,  H04L7/08

Abstract: A communication system, clock generation circuit, and method are provided for receiving jitter upon data and to generate a clock reference that does not contain the received jitter. The clock reference can be used either by a digital subsystem of a communication system node, or can be transmitted as substantially jitter-free data from that node to a downstream node of the communication system. Instead of recovering the clock reference from the data having jitter, a pattern is regularly defined within the data stream preferably at periodic, timed intervals. The data pattern may be made up of a series of non-transitions which, regardless of any jitter in the data itself, does not impute any jitter onto a phase-locked loop triggered from an edge of the non-transitioning data pattern. Using the edge as a reference point, a jitter-free clocking signal can be derived at the same frequency as a clocking signal which would normally be produced from the jitter-induced data.

Abstract translation: 提供通信系统，时钟发生电路和方法，用于在数据上接收抖动并产生不包含接收到的抖动的时钟参考。 时钟参考可以由通信系统节点的数字子系统使用，或者可以作为基本上无抖动的数据从该节点传送到通信系统的下游节点。 代替从具有抖动的数据恢复时钟参考，优选地以周期性的定时间隔在数据流内规则地定义模式。 数据模式可以由一系列非转换构成，无论数据本身中的任何抖动如何，都不会将任何抖动归因于从非转换数据模式的边沿触发的锁相环。 使用边缘作为参考点，可以以与通常由抖动引起的数据产生的时钟信号相同的频率导出无抖动时钟信号。

公开(公告)号：US07634694B2

公开(公告)日：2009-12-15

申请号：US10966254

申请日：2004-10-15

Applicant: Christopher M. Green ,  David J. Knapp ,  Horace C. Ho

Inventor： Christopher M. Green ,  David J. Knapp ,  Horace C. Ho

IPC: G06F11/00

CPC classification number: H04L25/03866 ,  H04L1/0061

Abstract: A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form. The scrambler is preferably placed before an encoder in the transmission path to minimize data dependent, low frequency jitter. The encoder is used to place a coding violation into the frame to signal the beginning of each frame, and to encode the parity with an offset against any DC accumulation of the coding violation and the scrambled payload to eliminate all DC accumulation (baseline wander) within each frame.

Abstract translation: 提供了一种用于发送和接收比特序列的通信系统，以及用于传送该比特序列的方法。 通信系统包括发送电路和接收电路。 在发送电路内是扰码器，其包括移位寄存器，使能电路和输出电路。 移位寄存器临时存储比特序列中的n位，并且使能电路使移位寄存器存储仅在帧的有效载荷部分内出现的位。 输出电路包括反馈和n级内的几个抽头，用于对从移位寄存器输出的n位序列内的逻辑值进行加扰，因此在大多数情况下有效地防止位序列超过n个相同逻辑值。 在接收电路内，还具有移位寄存器，使能电路和输出电路的解扰器。 解扰器将加扰的数据重新编译成其原始形式。 扰频器优选地放置在传输路径中的编码器之前，以最小化与数据有关的低频抖动。 编码器用于将编码违规发送到帧中以用信号通知每个帧的开始，并且将奇偶校验编码为针对编码违规和加扰有效载荷的任何DC积累的偏移，以消除所有的DC积累（基线漂移） 每一帧。

公开(公告)号：US07631176B2

公开(公告)日：2009-12-08

申请号：US11459413

申请日：2006-07-24

Applicant: Raphael Weiss ,  Richard E. Wahler ,  John D. Virzi ,  Randy B. Goldberg

Inventor： Raphael Weiss ,  Richard E. Wahler ,  John D. Virzi ,  Randy B. Goldberg

IPC: G06F9/00 ,  H03L7/00

CPC classification number: H05K1/0266 ,  H05K1/0268 ,  H05K1/18 ,  H05K2201/09927

Abstract: A resistor/capacitor identification detection (RCID) circuit may provide system level identification of hardware (e.g. circuit board ID) through a single pin interface, by identifying up to a specified number of more than two quantized RC time constant states by measuring the discharge and charge times of an external RC circuit coupled to the single pin. The RCID circuit may initiate the discharge followed by a charging of the external RC circuit. The signal developed at the signal pin may be provided to the input of a threshold detector, with the threshold set at a specified percentage of a supply voltage used for operating the RCID circuit. The digitized output of the threshold detector may be used to gate a counter, after having been filtered through an input glitch rejection filter. A resolution of the counter may be determined by a high frequency clock used for clocking the counter. The numeric values of the charge and discharge times may be stored in data registers comprised in the RCID circuit.

Abstract translation: 电阻/电容器识别检测（RCID）电路可以通过单个引脚接口提供硬件（例如电路板ID）的系统级别识别，通过测量放电确定多达两个量化的RC时间常数状态， 连接到单个引脚的外部RC电路的充电时间。 RCID电路可以启动放电，然后对外部RC电路进行充电。 在信号引脚处产生的信号可以被提供给阈值检测器的输入端，阈值设定在用于操作RCID电路的电源电压的指定百分比。 阈值检测器的数字化输出可以在通过输入毛刺抑制滤波器滤波后用于对计数器进行选通。 计数器的分辨率可以由用于对计数器计时的高频时钟确定。 充电和放电时间的数值可以存储在RCID电路中包含的数据寄存器中。

公开(公告)号：US07631110B2

公开(公告)日：2009-12-08

申请号：US11417775

申请日：2006-05-03

Applicant: Alan D. Berenbaum ,  Raphael Weiss

Inventor： Alan D. Berenbaum ,  Raphael Weiss

IPC: G06F3/00 ,  G06F13/00

CPC classification number: G06F13/42 ,  G06F2213/0052

Abstract: An address assignment mechanism. A computer system may include one or more types of slave devices. Each slave device includes an internal device ID. Slave devices of the same type include the same internal device ID. The master device may broadcast a message through the use of a protocol to each of the slave devices to initiate an address assignment operation. Each of the slave devices determines whether the broadcast device ID included in the broadcast message matches the internal device ID associated with the slave device. If the broadcast device ID matches the internal device ID, the linear bus address included in the broadcast message is assigned to the slave device. The bit size of the linear bus address may be smaller than that of the broadcast device ID. After the address assignment operation, the master device may communicate with the slave device using the assigned linear bus address rather than the device ID.

Abstract translation: 地址分配机制。 计算机系统可以包括一种或多种类型的从设备。 每个从设备包括一个内部设备ID。 相同类型的从设备包括相同的内部设备ID。 主设备可以通过使用协议向每个从设备广播消息以发起地址分配操作。 每个从设备确定广播消息中包括的广播设备ID是否与从设备相关联的内部设备ID匹配。 如果广播设备ID与内部设备ID匹配，则广播消息中包括的线性总线地址被分配给从设备。 线性总线地址的位大小可能小于广播设备ID的位大小。 在地址分配操作之后，主设备可以使用分配的线性总线地址而不是设备ID与从设备进行通信。