公开(公告)号：US20180174841A1

公开(公告)日：2018-06-21

申请号：US15845530

申请日：2017-12-18

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker DUDEK

IPC: H01L21/18 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L21/187 ,  H01L21/02546 ,  H01L21/02573 ,  H01L21/26546 ,  H01L29/20 ,  H01L31/0304 ,  H01L31/184 ,  H01L33/0079

Abstract: A method for manufacturing a layer stack having a p+-substrate, a p−-layer, an n−-layer and a third layer. A first partial stack and a second partial stack is produced, and an upper side of the first partial stack is integrally bonded with an upper side of the second partial stack , and the first partial stack has at least the p+-substrate. The second partial stack has at least the n−-layer, and the p−-layer is produced by epitaxy or implantation on an upper side of the p+-substrate or by epitaxy on the n− layer. The p−-layer forms the upper side of the first partial stack or the second partial stack. The third layer is produced prior to or after the wafer bonding, and the n−-layer is produced after the wafer bonding by abrading an n−-substrate or prior to the wafer bonding on an n+-substrate.

公开(公告)号：US20220254937A1

公开(公告)日：2022-08-11

申请号：US17667316

申请日：2022-02-08

Applicant: 3-5 Power Electronics GmbH

Inventor： Jens KOWALSKY ,  Volker DUDEK ,  Riteshkumar BHOJANI

IPC: H01L29/868 ,  H01L29/20

Abstract: A stacked III-V semiconductor diode comprising or consisting of GaAs with a highly n-doped cathode layer, a highly p-doped anode layer and a drift region arranged between the cathode layer and the anode layer, wherein the drift region has a low n-doped drift layer and a low p-doped drift layer, the n-doped drift layer is arranged between the p-doped drift layer and the cathode layer, both drift layers each have a layer thickness of at least 5 μm and, along the respective layer thickness, have a dopant concentration maximum of not more than 8·1015 cm−3, the dopant concentration maxima of the two drift layers have a ratio of 0.1 to 10 to each other and a ratio of the layer thickness of the n-doped drift layer to the layer thickness of the p-doped drift layer is between 0.5 and 3.

公开(公告)号：US20220140088A1

公开(公告)日：2022-05-05

申请号：US17579122

申请日：2022-01-19

Applicant: AZUR SPACE Solar Power GmbH ,  3-5 Power Electronics GmbH

Inventor： Daniel FUHRMANN ,  Gregor KELLER ,  Clemens WAECHTER ,  Volker DUDEK

IPC: H01L29/15 ,  H01L29/06 ,  H01L29/10 ,  H01L29/201 ,  H01L29/861

Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

公开(公告)号：US11271117B2

公开(公告)日：2022-03-08

申请号：US16809292

申请日：2020-03-04

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker Dudek

IPC: H01L29/861 ,  H01L29/20

Abstract: A stacked high-blocking III-V power semiconductor diode, with a p+ or n+ substrate layer, a p− layer, an n− region with a layer thickness of 10 μm-150 μm, and an n+ or p+ layer, wherein all layers comprise a GaAs compound, a first metallic contact layer and a second metallic contact layer and a hard mask layer with at least one seed opening, wherein the hard mask layer is integrally bonded to the substrate layer or integrally bonded to the p− layer, the n− region extends within the seed opening and over an edge region, adjacent to the seed opening, of a top side of the hard mask layer and the n− region within the seed opening is integrally bonded to the p− layer or to the n+ substrate layer and in the edge region of the top side of the hard mask layer to the hard mask layer.

公开(公告)号：US10854760B2

公开(公告)日：2020-12-01

申请号：US16252137

申请日：2019-01-18

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker Dudek

IPC: H01L29/86 ,  H01L29/861 ,  H01L29/36 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

Abstract: A stacked III-V semiconductor diode having an n− layer having a first surface, a second surface, a dopant concentration of 1012 N/cm3 to 1017 N/cm3 and a layer thickness of 50 μm to 1,000 μm, a p+ layer, which is integrally connected to the first surface and has a dopant concentration of 5·1018 N/cm3 to 5·1020 N/cm3, an n+ layer, which is integrally connected to the second surface and has a dopant concentration of at least 1019 N/cm3. The p+ layer, the n− layer and the n+ layer each having a monolithic design and each being made up of a GaAs compound. The dopant concentration of the n− layer having a first value on the first surface and a second value on the second surface, and the second value of the dopant concentration being greater than the first value at least by a factor between 1.5 and 2.5.

公开(公告)号：US20200350407A1

公开(公告)日：2020-11-05

申请号：US16863483

申请日：2020-04-30

Applicant: AZUR SPACE Solar Power GmbH ,  3-5 Power Electronics GmbH

Inventor： Daniel FUHRMANN ,  Gregor KELLER ,  Clemens WAECHTER ,  Volker DUDEK

IPC: H01L29/15 ,  H01L29/201 ,  H01L29/10 ,  H01L29/861 ,  H01L29/06

Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

公开(公告)号：US10749044B2

公开(公告)日：2020-08-18

申请号：US16379008

申请日：2019-04-09

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker Dudek

IPC: H01L29/861 ,  H01L29/34 ,  H01L29/06 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66 ,  H01L21/18

Abstract: A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p+ region, an n− layer, and an n+ region. The p+ region, the n− layer, and the n+ region follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The n+ region or the p+ region is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the n− layer or of an intermediate layer adjacent to the n− layer and to the p+ region and the first and the second peripheral edges each have a width of at least 10 μm.

公开(公告)号：US10340394B2

公开(公告)日：2019-07-02

申请号：US15934094

申请日：2018-03-23

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker Dudek

IPC: H01L29/861 ,  H01L29/20 ,  H01L29/36 ,  H01L29/32 ,  H01L29/872 ,  H01L29/66

Abstract: A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n−-layer with a dopant concentration of 1012-1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n−-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n−-layer and the p+-layer and materially bonded with an upper side and a lower side.

公开(公告)号：US10263124B2

公开(公告)日：2019-04-16

申请号：US15812432

申请日：2017-11-14

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker Dudek

IPC: H01L21/30 ,  H01L29/872 ,  H01L29/207 ,  H01L21/18 ,  H01L29/06 ,  H01L29/36 ,  H01L29/66 ,  H01L29/861

Abstract: A stacked III-V semiconductor diode having an n+ substrate with a dopant concentration of at least 1019 cm−3 and a layer thickness of 50-400 μm, an n− layer with a dopant concentration of 1012-1016 cm−3 and a layer thickness of 10-300 μm, a p+ layer with a dopant concentration of 5·1018-5·1020 cm−3, including a GaAs compound and with a layer thickness greater than 2 μm, wherein the n+ substrate and the n− layer are integrally joined to one another. A doped intermediate layer with a layer thickness of 1-50 μm and a dopant concentration of 1012-1017 cm−3 is arranged between the n− layer and the p+ layer, and the intermediate layer is integrally joined to the n− layer and to the p+ layer.

公开(公告)号：US20180277686A1

公开(公告)日：2018-09-27

申请号：US15934094

申请日：2018-03-23

Applicant: 3-5 Power Electronics GmbH

Inventor： Volker DUDEK

IPC: H01L29/861 ,  H01L29/20 ,  H01L29/36

CPC classification number: H01L29/8613 ,  H01L21/187 ,  H01L29/20 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66204 ,  H01L29/861 ,  H01L29/872

Abstract: A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n−-layer with a dopant concentration of 1012-1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n−-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n−-layer and the p+-layer and materially bonded with an upper side and a lower side.