公开(公告)号：US06660592B2

公开(公告)日：2003-12-09

申请号：US10160299

申请日：2002-05-29

Applicant: Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

Inventor： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

IPC: H01L21336

CPC classification number: H01L29/7813 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiment of the present invention are directed to improving the performance of a DMOS transistor. A method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate, and implanting first conductive dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form a first doping region. An insulating layer is deposited over the semiconductor substrate; and selectively etching the insulating layer to form a source contact window over a central portion of the first doping region and to leave an insulator structure above the trenched gate. The source contact window of the insulating layer has an enlarged top portion which is larger in size than a bottom portion of the source contact window closer to the first doping region than the enlarged top portion. The enlarged top portion is typically bowl-shaped. Second conductive dopants are implanted through the source contact window to form a second doping region in the central portion of the first doping region.

公开(公告)号：US08368140B2

公开(公告)日：2013-02-05

申请号：US12630088

申请日：2009-12-03

Applicant: Chiao-Shun Chuang

Inventor： Chiao-Shun Chuang

IPC: H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/0727

Abstract: In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction.

Abstract translation: 在一个实施例中，本发明包括半导体器件。 半导体器件包括第一半导体区域，第二半导体区域和沟槽区域。 第一半导体区域是第一导电类型和第一电导率浓度。 沟槽区域包括与第一半导体区域接触以形成金属 - 半导体结的金属层。 第二半导体区域与具有第二导电类型和第二电导率浓度的第一半导体区域相邻。 第二半导体区域与第一半导体区域形成PN结，并且沟槽区域具有使得金属 - 半导体结接近PN结的深度。

公开(公告)号：US06989306B2

公开(公告)日：2006-01-24

申请号：US10771808

申请日：2004-02-03

Applicant: Chiao-Shun Chuang ,  Hsin-Huang Hsieh ,  Mao-Song Tseng ,  Chien-Ping Chang

Inventor： Chiao-Shun Chuang ,  Hsin-Huang Hsieh ,  Mao-Song Tseng ,  Chien-Ping Chang

IPC: H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7813

Abstract: Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial layer is then selectively etched to form a plurality of DMOS trenches therein. Thereafter, a gate oxide layer is formed over exposed surfaces in the body region and a termination oxide layer is formed to encircle the body region. Afterward, a polysilicon layer is deposited over all the exposed surfaces, and then selectively etched to form a plurality of poly gates in the DMOS trenches and a polysilicon plate having an extending portion toward the body region over the termination oxide layer. By using the termination polysilicon layer as an implantation mask, sources are formed in the body region. Afterward, an isolation layer and a source metal contact layer are deposited over the structure, in which the isolation layer is utilized to protect the polysilicon gates, and also the source metal contact layer is utilized to ground both the body region and the polysilicon plate.

Abstract translation: 本发明的实施例提供了一种DMOS器件的端接结构及其形成方法。 在形成端接结构时，提供其上形成有外延层的硅衬底。 然后选择性地蚀刻通过掺杂外延层限定的体区，以在其中形成多个DMOS沟槽。 此后，在体区域中的暴露表面上形成栅极氧化物层，并且形成终止氧化物层以环绕身体区域。 之后，在所有暴露的表面上沉积多晶硅层，然后选择性地蚀刻以在DMOS沟槽中形成多个多晶硅栅极，以及在端接氧化物层上具有朝向主体区域的延伸部分的多晶硅板。 通过使用终止多晶硅层作为注入掩模，在体区域中形成源。 之后，在结构上沉积隔离层和源极金属接触层，其中隔离层用于保护多晶硅栅极，并且源极金属接触层用于接地体区域和多晶硅板。

公开(公告)号：US20050199952A1

公开(公告)日：2005-09-15

申请号：US11056450

申请日：2005-02-11

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L31/119

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.

公开(公告)号：US06821913B2

公开(公告)日：2004-11-23

申请号：US10232260

申请日：2002-08-29

Applicant: Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

Inventor： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

IPC: H01L2131

CPC classification number: H01L29/66734 ,  H01L21/0274 ,  H01L21/76224 ,  H01L29/42368

Abstract: Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching. The patterned mask oxide layer and a portion of the first oxide layer are removed to leave a remaining first oxide layer at the bottom of the trench. The remaining photoresist layer is removed. A second oxide layer is formed on the substrate covering at least the remaining first oxide layer to form the dual oxide layers at the bottom of the trench.

Abstract translation: 本发明的实施例涉及一种用于在衬底的沟槽的底部形成双重氧化物层的改进方法。 衬底具有包括底部和侧壁的沟槽。 可以通过在衬底上形成掩模氧化物层来形成沟槽; 限定所述掩模氧化物层以形成图案化掩模氧化物层并暴露所述衬底的部分表面以形成窗口; 并且使用图案化的掩模氧化物层作为蚀刻掩模以在窗口中形成沟槽。 第一氧化物层形成在衬底的沟槽的侧壁和底部上。 在衬底上形成光刻胶层，填充衬底的沟槽。 该方法还包括部分地蚀刻光致抗蚀剂层以在沟槽中留下残留的光致抗蚀剂层。 剩余的光致抗蚀剂层的高度低于沟槽的深度。 在部分蚀刻之后进行剩余光致抗蚀剂层的固化处理。 图案化的掩模氧化物层和第一氧化物层的一部分被去除以在沟槽的底部留下剩余的第一氧化物层。 去除剩余的光致抗蚀剂层。 在衬底上形成第二氧化物层，至少覆盖剩余的第一氧化物层，以在沟槽的底部形成双氧化层。