公开(公告)号：US06821913B2

公开(公告)日：2004-11-23

申请号：US10232260

申请日：2002-08-29

申请人： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

发明人： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

IPC分类号： H01L2131

CPC分类号： H01L29/66734 ,  H01L21/0274 ,  H01L21/76224 ,  H01L29/42368

摘要： Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching. The patterned mask oxide layer and a portion of the first oxide layer are removed to leave a remaining first oxide layer at the bottom of the trench. The remaining photoresist layer is removed. A second oxide layer is formed on the substrate covering at least the remaining first oxide layer to form the dual oxide layers at the bottom of the trench.

摘要翻译： 本发明的实施例涉及一种用于在衬底的沟槽的底部形成双重氧化物层的改进方法。 衬底具有包括底部和侧壁的沟槽。 可以通过在衬底上形成掩模氧化物层来形成沟槽; 限定所述掩模氧化物层以形成图案化掩模氧化物层并暴露所述衬底的部分表面以形成窗口; 并且使用图案化的掩模氧化物层作为蚀刻掩模以在窗口中形成沟槽。 第一氧化物层形成在衬底的沟槽的侧壁和底部上。 在衬底上形成光刻胶层，填充衬底的沟槽。 该方法还包括部分地蚀刻光致抗蚀剂层以在沟槽中留下残留的光致抗蚀剂层。 剩余的光致抗蚀剂层的高度低于沟槽的深度。 在部分蚀刻之后进行剩余光致抗蚀剂层的固化处理。 图案化的掩模氧化物层和第一氧化物层的一部分被去除以在沟槽的底部留下剩余的第一氧化物层。 去除剩余的光致抗蚀剂层。 在衬底上形成第二氧化物层，至少覆盖剩余的第一氧化物层，以在沟槽的底部形成双氧化层。

公开(公告)号：US06657263B2

公开(公告)日：2003-12-02

申请号：US09896205

申请日：2001-06-28

申请人： Cheng-Tsung Ni

发明人： Cheng-Tsung Ni

IPC分类号： H01L2976

CPC分类号： H01L29/66628 ,  H01L21/76838 ,  H01L21/76877 ,  H01L29/66545 ,  H01L29/7834

摘要： A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconnect contact windows, and is connected to other transistors and other IC components through interconnects formed on top of such self-aligned contact windows.

摘要翻译： 一种在包括MOS晶体管和其它IC组件的衬底上制造IC器件的方法。 IC器件的每个晶体管包括升高的源电极，升高的漏电极，双栅极电极和自对准的互连接触窗口，并且通过在这样的自对准顶部上形成的互连而连接到其它晶体管和其它IC部件 联系窗口。

公开(公告)号：US06563166B1

公开(公告)日：2003-05-13

申请号：US09523064

申请日：2000-03-10

申请人： Cheng-Tsung Ni

发明人： Cheng-Tsung Ni

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A memory device includes a first memory cell and a second memory cell both controlled by a common control gate. The device includes: a substrate; first and second stacks each including an insulating layer formed over the substrate, a first conductive layer formed over the insulating layer and providing a select gate, and a first dielectric layer formed over the first conductive layer, each of the stacks also including an inner sidewall and an outer sidewall, the. stacks being separated by a common area of the substrate, the inner and outer sidewalls of the stacks being coated with a second dielectric layer; first and second spacers formed adjacent the inner sidewalls of the first and second stacks respectively, the first and second spacers being separated by a medial portion of the common source area of the substrate, each of the spacers. including a tunnel oxide layer disposed over the substrate, and a second conductive layer disposed over the tunnel oxide layer and providing a floating gate; first and second drain regions formed in the substrate proximate the outer sidewalls of the first and second stacks; a common source region formed beneath the common source area; a third dielectric layer disposed over the first and second spacers, and the first and second stacks; and a third conductive layer, disposed over inner portions of the first and second select gate stacks, and forming the common control gate.

摘要翻译： 存储器件包括由公共控制栅极控制的第一存储器单元和第二存储单元。 该装置包括：基板; 第一和第二堆叠，每个堆叠包括形成在衬底上的绝缘层，形成在绝缘层上并提供选择栅极的第一导电层和形成在第一导电层上的第一电介质层，每个堆叠还包括内侧壁 和外侧壁。 堆叠由衬底的公共区域分开，堆叠的内侧壁和外侧壁涂覆有第二介电层; 分别与第一和第二堆叠的内侧壁相邻形成的第一和第二间隔件，第一和第二间隔件被衬底的公共源区域的中间部分分隔开，每个间隔件。 包括设置在所述衬底上的隧道氧化物层，以及设置在所述隧道氧化物层上并提供浮动栅极的第二导电层; 形成在靠近第一和第二堆叠的外侧壁的基板中的第一和第二漏极区域; 形成在共同源极区域下面的共同源极区域; 设置在第一和第二间隔物上的第三电介质层，以及第一和第二堆叠; 以及第三导电层，设置在第一和第二选择栅极堆叠的内部部分上，并形成公共控制栅极。

公开(公告)号：US06284578B1

公开(公告)日：2001-09-04

申请号：US09534699

申请日：2000-03-24

申请人： Cheng-Tsung Ni

发明人： Cheng-Tsung Ni

IPC分类号： H01L21338

CPC分类号： H01L29/66628 ,  H01L21/76838 ,  H01L21/76877 ,  H01L29/66545 ,  H01L29/7834

摘要： A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconnect contact windows, and is connected to other transistors and other IC components through interconnects formed on top of such self-aligned contact windows.

摘要翻译： 一种在包括MOS晶体管和其它IC组件的衬底上制造IC器件的方法。 IC器件的每个晶体管包括升高的源电极，升高的漏电极，双栅极电极和自对准的互连接触窗口，并且通过在这样的自对准顶部上形成的互连而连接到其它晶体管和其它IC部件 联系窗口。

公开(公告)号：US6150244A

公开(公告)日：2000-11-21

申请号：US467086

申请日：1999-12-10

申请人： Cheng-Tsung Ni

发明人： Cheng-Tsung Ni

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/60 ,  H01L21/22

CPC分类号： H01L21/76897 ,  H01L29/41783 ,  H01L29/66575 ,  H01L21/2257

摘要： A process for fabricating a semiconductor device comprising a raised source and drain. A semiconductor device is fabricated by a process comprising the following steps: forming active regions separated by isolation regions; forming at each active region a gate electrode structure; depositing a first dielectric layer and a second dielectric layer; removing the top portion of the second dielectric layer to expose the portion of the first dielectric layer that covers the gate electrode structure; forming on the substrate a patterned resist layer to mask portions of the second dielectric layer; forming trenches next to the gate electrode structure by removing the unmasked portions of the second dielectric layer; filling the trenches with a conductor; doping the conductor with dopants; and driving the dopants into the substrate to form the raised source and drain.

摘要翻译： 一种用于制造包括升高的源极和漏极的半导体器件的工艺。 通过包括以下步骤的方法制造半导体器件：形成由隔离区隔开的有源区; 在每个有源区形成栅电极结构; 沉积第一介电层和第二介电层; 去除第二电介质层的顶部以暴露覆盖栅电极结构的第一介电层的部分; 在所述衬底上形成图案化的抗蚀剂层以掩蔽所述第二介电层的部分; 通过去除所述第二介电层的未掩模部分，在所述栅电极结构旁边形成沟槽; 用导体填充沟槽; 用掺杂剂掺杂导体; 并将掺杂剂驱动到衬底中以形成升高的源极和漏极。

公开(公告)号：US6008106A

公开(公告)日：1999-12-28

申请号：US915693

申请日：1997-08-21

申请人： Tuby Tu ,  Chen Kuang-Chao ,  Cheng-Tsung Ni ,  Chih-Hsun Chu

发明人： Tuby Tu ,  Chen Kuang-Chao ,  Cheng-Tsung Ni ,  Chih-Hsun Chu

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/7621

摘要： A method of forming isolation region of an integrated circuit by using rough oxide mask is described. First, a layer of first dielectric is formed on the surface of a silicon substrate. The first dielectric layer is then patterned to define active device region and isolation region. Next, a very thin layer of silicon dioxide is formed over the silicon substrate surface, followed by depositing a layer of rough oxide with proper grain size overlaying the silicon dioxide layer. By using rough oxide grains as an etching mask, the silicon dioxide layer and the silicon substrate underneath are spontaneously etched to form multiple trenches in the isolation region. Next, the rough oxide grains and silicon dioxide layers are stripped. Then, filed oxidation is performed to complete the field oxide isolation formation.

摘要翻译： 描述了通过使用粗略氧化物掩膜形成集成电路的隔离区域的方法。 首先，在硅衬底的表面上形成第一电介质层。 然后将第一介电层图案化以限定有源器件区域和隔离区域。 接下来，在硅衬底表面上形成非常薄的二氧化硅层，随后沉积具有覆盖二氧化硅层的适当晶粒尺寸的粗大氧化物层。 通过使用粗糙氧化物晶粒作为蚀刻掩模，自发蚀刻下面的二氧化硅层和硅衬底，以在隔离区域中形成多个沟槽。 接下来，剥离粗糙的氧化物颗粒和二氧化硅层。 然后进行归档氧化以完成场氧化物隔离层。

公开(公告)号：US5804493A

公开(公告)日：1998-09-08

申请号：US540773

申请日：1995-10-11

申请人： Minn-Horng Juang ,  Cheng-Tsung Ni ,  Chih-Hsien Wang

发明人： Minn-Horng Juang ,  Cheng-Tsung Ni ,  Chih-Hsien Wang

IPC分类号： H01L21/762 ,  H01L27/105

CPC分类号： H01L21/76202

摘要： A method for preventing substrate damage during semiconductor fabrication, comprising, forming a pad oxide layer on the substrate, depositing a polysilicon buffer layer on the pad oxide layer, ion-implanting fluorine into the polysilicon buffer layer, depositing a silicon nitride layer on the polysilicon buffer layer, defining an active region in the substrate, forming a local oxide layer beside the surface of the active region, removing the silicon nitride layer, removing the polysilicon buffer layer by dry etching, and etching the pad oxide layer to expose the substrate surface of active region.

摘要翻译： 一种用于在半导体制造期间防止衬底损伤的方法，包括：在所述衬底上形成衬垫氧化物层，在所述衬垫氧化物层上沉积多晶硅缓冲层，将氟离子注入到所述多晶硅缓冲层中，在所述多晶硅缓冲层上沉积氮化硅层 缓冲层，在衬底中限定有源区，在有源区的表面旁边形成局部氧化层，去除氮化硅层，通过干蚀刻去除多晶硅缓冲层，并蚀刻衬垫氧化物层以露出衬底表面 的活跃地区。

公开(公告)号：US5972754A

公开(公告)日：1999-10-26

申请号：US95674

申请日：1998-06-10

申请人： Cheng-Tsung Ni ,  Chih-Hsun Chu

发明人： Cheng-Tsung Ni ,  Chih-Hsun Chu

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66613 ,  H01L29/66621 ,  H01L29/7834 ,  H01L21/2257

摘要： A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.

公开(公告)号：US06660592B2

公开(公告)日：2003-12-09

申请号：US10160299

申请日：2002-05-29

申请人： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

发明人： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/7802

摘要： Embodiment of the present invention are directed to improving the performance of a DMOS transistor. A method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate, and implanting first conductive dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form a first doping region. An insulating layer is deposited over the semiconductor substrate; and selectively etching the insulating layer to form a source contact window over a central portion of the first doping region and to leave an insulator structure above the trenched gate. The source contact window of the insulating layer has an enlarged top portion which is larger in size than a bottom portion of the source contact window closer to the first doping region than the enlarged top portion. The enlarged top portion is typically bowl-shaped. Second conductive dopants are implanted through the source contact window to form a second doping region in the central portion of the first doping region.

公开(公告)号：US06228729B1

公开(公告)日：2001-05-08

申请号：US09514455

申请日：2000-02-25

申请人： Cheng-Tsung Ni

发明人： Cheng-Tsung Ni

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L21/76838 ,  H01L21/76877 ,  H01L29/66545

摘要： A process for fabricating a semiconductor device comprising a gate electrode, a raised source, a raised drain and an interconnect inlaid into an isolation region. A semiconductor device is fabricated by a process comprising the following steps: forming sequentially a first dielectric layer and a first conductor layer on the substrate; forming one or more inset isolation regions in the substrate; filling each inset isolation region with an isolation layer; forming a second dielectric layer on top of the first conductor layer and the isolation layers; forming simultaneously a first and a second trench; forming a plurality of cavities at the bottom of the first trench; filling each cavity with a second conductor layer; forming a plurality of dielectric sidewalls and a dielectric bottom layer in the first trench; forming the gate electrode and the interconnect by filling the first and second trenches with a third conductor layer; doping the first conductor layer with dopants; and forming the raised source and the raised drain by driving the dopants into the surface region of the substrate.

摘要翻译： 一种用于制造半导体器件的方法，该半导体器件包括嵌入到隔离区中的栅电极，凸起源，升高漏极和互连。 通过包括以下步骤的方法制造半导体器件：在衬底上依次形成第一电介质层和第一导体层; 在衬底中形成一个或多个插入隔离区; 用隔离层填充每个插入隔离区; 在所述第一导体层和隔离层的顶部上形成第二电介质层; 同时形成第一和第二沟槽; 在第一沟槽的底部形成多个空腔; 用第二导体层填充每个空腔; 在所述第一沟槽中形成多个电介质侧壁和电介质底层; 通过用第三导体层填充第一和第二沟槽来形成栅电极和互连; 用掺杂剂掺杂第一导体层; 以及通过将掺杂剂驱动到衬底的表面区域中而形成升高的源极和高的漏极。