公开(公告)号：US20100181847A1

公开(公告)日：2010-07-22

申请号：US12358215

申请日：2009-01-22

Applicant: Shen-Yu Huang ,  Chih-Ching Lin

Inventor： Shen-Yu Huang ,  Chih-Ching Lin

IPC: H05K7/06

CPC classification number: H01L27/0207 ,  H01L23/5223 ,  H01L23/5286 ,  H01L28/20 ,  H01L2924/0002 ,  H03K19/00346 ,  H01L2924/00

Abstract: A method for reducing a supply voltage drop in a digital circuit block, where the digital circuit block includes a first conducting segment coupled to a first supply voltage, a second conducting segment coupled to a second supply voltage, and a digital logic coupled between the first conducting segment and the second conducting segment, the method including: constructing a third conducting segment connected to the first conducting segment and not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer; and constructing a fourth conducting segment electrically connected to the second conducting segment and not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at a second conducting layer, and whereby a capacitive element is formed between the first portion and the second portion.

Abstract translation: 一种用于减少数字电路块中的电源电压降的方法，其中所述数字电路块包括耦合到第一电源电压的第一导电段，耦合到第二电源电压的第二导电段和耦合在所述第一电源电压之间的数字逻辑 导电段和第二导电段，所述方法包括：构造连接到所述第一导电段并且未电连接到所述第二导电段的第三导电段，其中所述第三导电段被配置为具有位于第一导电段 层; 以及构造电连接到所述第二导电段并且不电连接到所述第一导电段的第四导电段，其中所述第四导电段被配置为具有位于第二导电层的第二部分， 第一部分和第二部分。

公开(公告)号：US20080254589A1

公开(公告)日：2008-10-16

申请号：US11829067

申请日：2007-07-26

Applicant: Jen-Jui Huang ,  Chih-Ching Lin

Inventor： Jen-Jui Huang ,  Chih-Ching Lin

IPC: H01L21/20

CPC classification number: H01L29/66181 ,  H01L27/1087

Abstract: A method for manufacturing collars of deep trench capacitors includes providing a substrate with a deep trench in which there is a trench capacitor in the bottom; forming an inner wall layer completely covering the deep trench and the substrate; forming a hard mask layer on the surface of the inner wall layer; performing a selective implanting but not on the hard mask layer on the wall of the deep trench; performing a selective wet etching to remove the not implanted hard mask layer; and performing an anisotropic dry etching to substantially remove the inner wall layer on the bottom of the deep trench so as to partially expose the trench capacitor and to substantially retain the collars of the deep trench capacitors intact.

Abstract translation: 一种用于制造深沟槽电容器的套环的方法包括：向衬底提供深沟槽，其中在底部存在沟槽电容器; 形成完全覆盖深沟槽和衬底的内壁层; 在内壁层的表面上形成硬掩模层; 执行选择性植入，但不在深沟槽的壁上的硬掩模层上进行; 执行选择性湿蚀刻以去除未注入的硬掩模层; 并进行各向异性干蚀刻以基本上去除深沟槽底部的内壁层，以便部分地暴露沟槽电容器并且基本上保持深沟槽电容器的套环完好无损。

公开(公告)号：US20080172105A1

公开(公告)日：2008-07-17

申请号：US11896879

申请日：2007-09-06

Applicant: Chih-Ching Lin ,  Chyi-Ran Lee

Inventor： Chih-Ching Lin ,  Chyi-Ran Lee

IPC: A61B18/18

CPC classification number: A61N5/0613 ,  A61N2005/066

Abstract: A method for preventing and/or ameliorating inflammation. The method comprises irradiating a biological subject with an electromagnetic wave from an emitter, wherein the electromagnetic wave has a wavelength of about 1.5 to 100 μm μm, and the biological subject can be a peripheral vascular disease patient. Additionally, the method of the invention can improve the access blood flow and unassisted patency of arteriovenous fistula in hemodialysis patients.

Abstract translation: 一种预防和/或改善炎症的方法。 该方法包括用来自发射器的电磁波照射生物学对象，其中电磁波具有大约1.5至100个妈妈的波长，生物学对象可以是外周血管疾病患者。 此外，本发明的方法可以改善血液透析患者的动静脉瘘的通路血流量和无辅助通畅。

公开(公告)号：US07067418B2

公开(公告)日：2006-06-27

申请号：US10908824

申请日：2005-05-27

Applicant: Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

Inventor： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

IPC: H01L21/4763

CPC classification number: H01L21/7685 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76837

Abstract: A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

公开(公告)号：US20130037934A1

公开(公告)日：2013-02-14

申请号：US13205648

申请日：2011-08-09

Applicant: Chih-Ching Lin ,  Ya-Ting Chang ,  Chia-Lin Chuang

Inventor： Chih-Ching Lin ,  Ya-Ting Chang ,  Chia-Lin Chuang

IPC: H01L23/48

CPC classification number: H01L23/5286 ,  H01L23/5223 ,  H01L24/05

Abstract: An integrated circuit chip includes a power/ground interconnection network in a topmost metal layer over a semiconductor substrate and at least a bump pad on/over the power/ground interconnection network. The power/ground mesh interconnection network includes a first power/ground line connected to the bump pad and extending along a first direction, and a connection portion connected to the bump pad and extending along a second direction.

Abstract translation: 集成电路芯片包括位于半导体衬底上的最顶层金属层中的电源/接地互连网络，以及至少在电力/接地互连网络上/之上的凸块焊盘。 电源/接地网状互连网络包括连接到凸块焊盘并沿着第一方向延伸的第一电源/接地线，以及连接到凸块焊盘并沿第二方向延伸的连接部分。

公开(公告)号：US20130017687A1

公开(公告)日：2013-01-17

申请号：US13183358

申请日：2011-07-14

Applicant: Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/306

CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/32137

Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

Abstract translation: 提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上 垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

公开(公告)号：US20120056488A1

公开(公告)日：2012-03-08

申请号：US13298315

申请日：2011-11-17

Applicant: Shen-Yu Huang ,  Chih-Ching Lin

Inventor： Shen-Yu Huang ,  Chih-Ching Lin

IPC: H02J1/02 ,  H05K3/00

CPC classification number: H01L27/0207 ,  H01L23/5223 ,  H01L23/5286 ,  H01L28/20 ,  H01L2924/0002 ,  H03K19/00346 ,  H01L2924/00

Abstract: A digital circuit block includes first to fourth conducting segments, a digital logic, first and second conducting layers, and a dielectric layer. The first and second conducting segments are coupled to first and second supply voltages, respectively. The digital logic and dielectric layer are between the first and second conducting segments. The third conducting segment includes a first end electrically connected to the first conducting segment, a second end not electrically connected to the second conducting segment, and a first portion located at the first conducting layer. The fourth conducting segment includes a first end electrically connected to the second conducting segment, a second end not electrically connected to the first conducting segment, and a second portion located at the second conducting layer. The first and second portions and dielectric layer are formed a first capacitive element to reduce the supply voltage drop between the first and second supply voltages.

Abstract translation: 数字电路块包括第一至第四导电段，数字逻辑，第一和第二导电层以及电介质层。 第一和第二导电段分别耦合到第一和第二电源电压。 数字逻辑和电介质层位于第一和第二导电段之间。 第三导电段包括电连接到第一导电段的第一端，不电连接到第二导电段的第二端和位于第一导电层的第一部分。 第四导电段包括电连接到第二导电段的第一端，不电连接到第一导电段的第二端和位于第二导电层的第二部分。 第一和第二部分和电介质层形成第一电容元件以减小第一和第二电源电压之间的电源电压降。

公开(公告)号：US20090249273A1

公开(公告)日：2009-10-01

申请号：US12060298

申请日：2008-04-01

Applicant: Tung-Kai Tsai ,  Chih-Ching Lin

Inventor： Tung-Kai Tsai ,  Chih-Ching Lin

IPC: G06F17/50 ,  H03K19/003

CPC classification number: G06F17/5068 ,  G06F2217/72 ,  H01L27/0207 ,  H01L27/11807

Abstract: A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.

Abstract translation: 提供了一种布局电路，包括标准单元，备用单元，组合连接单元和普通填充单元。 标准单元被布置并布置在布局区域上。 在布局区域中添加备用单元，并在稍后添加或更改功能时提供替换其中一个标准单元。 组合的领带单元被添加在布局区域上。 正常填充单元被添加到布局区域的其余部分。 组合式连接单元包括连接高电路，连接低电路和电容电路。 一些标准单元设置在至少一个组合的连接单元附近，以避免组合连接单元与替换的标准单元之间的路由拥塞。 还提供了电路布局方法。

公开(公告)号：US20090124079A1

公开(公告)日：2009-05-14

申请号：US12042347

申请日：2008-03-05

Applicant: Jen-Jui Huang ,  Chih-Ching Lin ,  Kuo-Chung Chen

Inventor： Jen-Jui Huang ,  Chih-Ching Lin ,  Kuo-Chung Chen

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L27/10888

Abstract: A method for fabricating a conductive plug includes the steps of providing a substrate having at least a gate structure thereon, a first dielectric layer covering a surface of the substrate, a second dielectric layer disposed on the first dielectric layer, and at least a metal line formed within the second dielectric layer; forming a hard mask plug on the second dielectric layer; forming a third dielectric layer covering the second dielectric layer and the hard mask plug; removing a portion of the third dielectric layer to expose the hard mask plug; removing the hard mask plug to form a plug hole; and forming the conductive plug within the plug hole to electrically connect with the gate structure.

Abstract translation: 一种用于制造导电插塞的方法包括以下步骤：提供其上具有至少栅极结构的衬底，覆盖衬底表面的第一介电层，设置在第一电介质层上的第二电介质层，以及至少金属线 形成在所述第二电介质层内; 在所述第二电介质层上形成硬掩模塞; 形成覆盖所述第二介电层和所述硬掩模塞的第三介电层; 去除所述第三电介质层的一部分以暴露所述硬掩模塞; 去除硬掩模塞以形成塞孔; 以及在所述插塞孔内形成所述导电插塞以与所述栅极结构电连接。

公开(公告)号：US20050048761A1

公开(公告)日：2005-03-03

申请号：US10646896

申请日：2003-08-25

Applicant: Chih-Ching Lin ,  Yi-Nan Chen

Inventor： Chih-Ching Lin ,  Yi-Nan Chen

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/76802 ,  H01L21/76865

Abstract: Disclosed is a method for forming conducting wire and contact opening in a semiconductor device. The method comprises steps of providing a substrate; forming a first dielectric layer on the substrate; digging a via in the first dielectric layer and filling metal therein; forming a conductor layer on the first dielectric including the via; forming a metal layer on the conductor layer; removing unnecessary portions of the conductor/metal layers to define recesses, with the left portions to form conducting wires; applying a second dielectric layer to fill the recesses and performing planarization thereto to expose the conducting wires; forming a third dielectric layer; forming photoresist of predetermined pattern on the third dielectric layer; removing predetermined portion of the third dielectric layer to form a contact opening; and removing the photoresist.

Abstract translation: 公开了一种在半导体器件中形成导线和接触开口的方法。 该方法包括提供衬底的步骤; 在所述基板上形成第一电介质层; 在第一电介质层中挖掘通孔并在其中填充金属; 在包括通孔的第一电介质上形成导体层; 在导体层上形成金属层; 去除导体/金属层的不需要的部分以限定凹部，其中左部分形成导线; 施加第二电介质层以填充凹部并对其进行平坦化以暴露导线; 形成第三电介质层; 在所述第三介电层上形成预定图案的光致抗蚀剂; 去除所述第三电介质层的预定部分以形成接触开口; 并去除光致抗蚀剂。