公开(公告)号：US09367655B2

公开(公告)日：2016-06-14

申请号：US13443568

申请日：2012-04-10

Applicant: I-Chang Shih ,  Chung-min Fu ,  Ying-Chou Cheng ,  Yung-Fong Lu ,  Feng-Yuan Chiu ,  Chiu Hsiu Chen

Inventor： I-Chang Shih ,  Chung-min Fu ,  Ying-Chou Cheng ,  Yung-Fong Lu ,  Feng-Yuan Chiu ,  Chiu Hsiu Chen

IPC: H01L21/66 ,  G06F17/50 ,  G03F7/20

CPC classification number: G06F17/5027 ,  G03F7/705 ,  H01L22/10 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.

Abstract translation: 本公开提供了一种方法。 该方法包括获得集成电路（IC）布局。 该方法包括提供抛光过程模拟模型。 该方法包括对IC布局执行光刻图案校验（LPC）处理。 LPC处理至少部分地使用抛光工艺模拟模型进行。 该方法包括响应于LPC过程检测IC布局上的可能问题区域。 该方法包括修改抛光过程仿真模型。 该方法包括重复执行LPC处理和使用改进的抛光处理模拟模型来检测可能的问题区域。

公开(公告)号：US08726200B2

公开(公告)日：2014-05-13

申请号：US13303374

申请日：2011-11-23

Applicant: Chung-Min Fu ,  Yung-Fong Lu ,  Wen-Ju Yang ,  Chin-Chang Hsu

Inventor： Chung-Min Fu ,  Yung-Fong Lu ,  Wen-Ju Yang ,  Chin-Chang Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70

Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

Abstract translation: 装置包括用于存储具有至少一个模板的模板库的机器可读存储介质。 该模板将包括通过多图案化IC的单层而形成的至少一个图案的第一布局图示。 该图案具有使用多个分别不同的光掩模形成的多个部分。 第一布局表示包括识别每个部分将要位于哪个光掩模上的数据。 电子设计自动化（EDA）工具包括被配置为接收电路的至少一部分的硬件描述语言表示并且生成具有多个多边形的电路的一部分的第二布局表示的处理器。 EDA工具具有匹配模块，其识别并输出多个部分中的一个或多个部分是否匹配多个多边形的子集的指示。

公开(公告)号：US08631372B2

公开(公告)日：2014-01-14

申请号：US13477153

申请日：2012-05-22

Applicant: Chi-Yeh Yu ,  Chung-Min Fu ,  Ping-Heng Yeh

Inventor： Chi-Yeh Yu ,  Chung-Min Fu ,  Ping-Heng Yeh

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5081

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.

Abstract translation: 计算机实现的方法包括访问存储在有形的，非暂时的机器可读介质中的3D-IC模型，在计算机处理器中处理该模型以产生包含在操作下的3D-IC的多个点处的温度的温度图 条件; 识别电迁移（EM）额定因子，以及从处理器计算和输出表示每个点处的温度依赖EM电流约束的数据。

公开(公告)号：US20130267047A1

公开(公告)日：2013-10-10

申请号：US13443568

申请日：2012-04-10

Applicant: I-Chang Shih ,  Chung-min Fu ,  Ying-Chou Cheng ,  Yung-Fong Lu ,  Feng-Yuan Chiu ,  Chiu Hsiu Chen

Inventor： I-Chang Shih ,  Chung-min Fu ,  Ying-Chou Cheng ,  Yung-Fong Lu ,  Feng-Yuan Chiu ,  Chiu Hsiu Chen

IPC: H01L21/66 ,  G06F17/50

CPC classification number: G06F17/5027 ,  G03F7/705 ,  H01L22/10 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.

Abstract translation: 本公开提供了一种方法。 该方法包括获得集成电路（IC）布局。 该方法包括提供抛光过程模拟模型。 该方法包括对IC布局执行光刻图案校验（LPC）处理。 LPC处理至少部分地使用抛光工艺模拟模型进行。 该方法包括响应于LPC过程检测IC布局上的可能问题区域。 该方法包括修改抛光过程仿真模型。 该方法包括重复执行LPC处理和使用改进的抛光处理模拟模型来检测可能的问题区域。

公开(公告)号：US20110016443A1

公开(公告)日：2011-01-20

申请号：US12763889

申请日：2010-04-20

Applicant: Chung-Min Fu ,  Meng-Fu You

Inventor： Chung-Min Fu ,  Meng-Fu You

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Embodiments of the present invention are a system, a computer program product, and a method for implementing an integrated circuit design. An embodiment is a method for implementing an integrated circuit design. The method comprises accessing an original electronic representation of an integrated circuit layout from a first user file, accessing a defined sensitivity index that characterizes an impact of the dummy pattern on the functional component, analyzing the impact of the dummy pattern on the functional component, determining whether the impact is within a limit of the sensitivity index, adjusting one of a plurality of features of the dummy pattern if the impact is not within the limit to form a generated electronic representation of a modified integrated circuit layout, and outputting the generated electronic representation to a second user file. The integrated circuit layout comprises a dummy pattern and a functional component.

Abstract translation: 本发明的实施例是一种用于实现集成电路设计的系统，计算机程序产品和方法。 实施例是用于实现集成电路设计的方法。 该方法包括从第一用户文件访问集成电路布局的原始电子表示，访问表征虚拟模式对功能组件的影响的定义的灵敏度指标，分析虚拟模式对功能组件的影响，确定 影响是否在灵敏度指标的极限内，如果影响不在限制内，则调整虚拟图案的多个特征之一以形成经修改的集成电路布局的生成的电子表示，并输出生成的电子表示 到第二个用户文件。 集成电路布局包括虚拟图案和功能部件。

公开(公告)号：US07356787B2

公开(公告)日：2008-04-08

申请号：US11099834

申请日：2005-04-06

Applicant: Jui-Jung Yan ,  Chung-Min Fu ,  Ricky Yang

Inventor： Jui-Jung Yan ,  Chung-Min Fu ,  Ricky Yang

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A system for defect simulation is provided. A defect layout generator generates a defect layout comprising a given number of spot defects of a given size. A processor first compares the defect layout and a provided circuit layout comprising a plurality of conductive regions. The processor further determines whether the spot defects are located on the conductive regions, and determines whether short-circuits and/or open circuits are caused by the spot defects in the conductive regions.

Abstract translation: 提供了一种用于缺陷模拟的系统。 缺陷布局生成器生成包括给定尺寸的给定数量的斑点缺陷的缺陷布局。 处理器首先比较缺陷布局和提供的包括多个导电区域的电路布局。 处理器还确定斑点缺陷是否位于导电区域上，并且确定短路和/或开路是否由导电区域中的斑点缺陷引起。

公开(公告)号：US20070276770A1

公开(公告)日：2007-11-29

申请号：US11486521

申请日：2006-07-13

Applicant: Chung-Min Fu ,  Yu-Chyi Harn

Inventor： Chung-Min Fu ,  Yu-Chyi Harn

IPC: G06F17/00

CPC classification number: G06Q30/0283 ,  G06Q10/04

Abstract: Aspects of the present invention provide a method and a system for predicting shrinkable yield for business assessment of integrated circuit design shrink. An assessment system is provided to determine cost benefits of a design shrink of an integrated circuit chip. A cost benefit analysis across different design shrink technologies is provided early in the process, so that business decisions regarding employment of design shrinks can be made as early as possible.

Abstract translation: 本发明的方面提供了一种用于预测集成电路设计业务评估收缩收益的方法和系统。 提供评估系统来确定集成电路芯片设计收缩的成本优势。 在早期提供不同设计收缩技术的成本效益分析，以便尽可能早地制定有关就业设计缩减的业务决策。