公开(公告)号：US11042811B2

公开(公告)日：2021-06-22

申请号：US15725600

申请日：2017-10-05

Applicant: D-Wave Systems Inc.

Inventor： Jason Rolfe ,  William G. Macready ,  Zhengbing Bian ,  Fabian A. Chudak

IPC: G06N10/00 ,  G06N3/04 ,  G06K9/00 ,  G06N3/08 ,  G06F15/80 ,  G06N20/00 ,  G06K9/62 ,  G06N20/10 ,  G06N7/00

Abstract: A computational system can include digital circuitry and analog circuitry, for instance a digital processor and a quantum processor. The quantum processor can operate as a sample generator providing samples. Samples can be employed by the digital processing in implementing various machine learning techniques. For example, the computational system can perform unsupervised learning over an input space, for example via a discrete variational auto-encoder, and attempting to maximize the log-likelihood of an observed dataset. Maximizing the log-likelihood of the observed dataset can include generating a hierarchical approximating posterior. Unsupervised learning can include generating samples of a prior distribution using the quantum processor. Generating samples using the quantum processor can include forming chains of qubits and representing discrete variables by chains.

公开(公告)号：US11031537B2

公开(公告)日：2021-06-08

申请号：US16380751

申请日：2019-04-10

Applicant: D-WAVE SYSTEMS INC.

Inventor： Richard G. Harris ,  Andrew J. Berkley ,  Jan Johansson ,  Mark Johnson ,  Mohammad Amin ,  Paul I. Bunyk

IPC: G06N99/00 ,  H01L39/22 ,  G06N10/00 ,  B82Y10/00 ,  H01L27/18

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

公开(公告)号：US11023821B2

公开(公告)日：2021-06-01

申请号：US15881260

申请日：2018-01-26

Applicant: D-WAVE SYSTEMS INC.

Inventor： Richard G. Harris ,  Kelly T. R. Boothby ,  Andrew D. King

IPC: G06N10/00 ,  H01L39/22 ,  H01L49/00 ,  H01L39/00

Abstract: A system and method of operation embeds a three-dimensional structure in a topology of an analog processor, for example a quantum processor. The analog processor may include a plurality of qubits arranged in tiles or cells. A number of qubits and communicatively coupled as logical qubits, each logical qubit which span across a plurality of tiles or cells of the qubits. Communicatively coupling between qubits of any given logical qubit can be implemented via application or assignment of a first ferromagnetic coupling strength to each of a number of couplers that communicatively couple the respective qubits in the logical qubit. Other ferromagnetic coupling strengths can be applied or assigned to couplers that communicatively couple qubits that are not part of the logical qubit. The first ferromagnetic coupling strength may be substantially higher than the other ferromagnetic coupling strengths.

公开(公告)号：US20210089884A1

公开(公告)日：2021-03-25

申请号：US16772094

申请日：2018-12-12

Applicant: D-WAVE SYSTEMS INC.

Inventor： William G. Macready ,  Jason T. Rolfe

IPC: G06N3/08 ,  G06N3/04 ,  G06N10/00 ,  G06K9/62

Abstract: Collaborative filtering systems based on variational autoencoders (VAEs) are provided. VAEs may be trained on row-wise data without necessarily training a paired VAE on column-wise data (or vice-versa), and may optionally be trained via minibatches. The row-wise VAE models the output of the corresponding column-based VAE as a set of parameters and uses these parameters in decoding. In some implementations, a paired VAE is provided which receives column-wise data and models row-wise parameters; each of the paired VAEs may bind their learned column- or row-wise parameters to the output of the corresponding VAE. The paired VAEs may optionally be trained via minibatches. Unobserved data may be explicitly modelled. Methods for performing inference with such VAE-based collaborative filtering systems are also disclosed, as are example applications to search and anomaly detection.

公开(公告)号：US20200380396A1

公开(公告)日：2020-12-03

申请号：US16878364

申请日：2020-05-19

Applicant: D-WAVE SYSTEMS INC.

Inventor： Jack R. Raymond

IPC: G06N7/00 ,  G06N10/00 ,  G01R29/26 ,  G01R33/24

Abstract: Calibration techniques for devices of analog processors to remove time-dependent biases are described. Devices in an analog processor exhibit a noise spectrum that spans a wide range of frequencies, characterized by 1/f spectrum. Offset parameters are determined assuming only a given power spectral density. The algorithm determines a model for a measurable quantity of a device in an analog processor associated with a noise process and an offset parameter, determines the form of the spectral density of the noise process, approximates the noise spectrum by a discrete distribution via the digital processor, constructs a probability distribution of the noise process based on the discrete distribution and evaluates the probability distribution to determine optimized parameter settings to enhance computational efficiency.

公开(公告)号：US20200293486A1

公开(公告)日：2020-09-17

申请号：US16859672

申请日：2020-04-27

Applicant: D-WAVE SYSTEMS INC.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H.S. Amin ,  Geordie Rose ,  David Grant ,  Miles F.H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06F15/80 ,  H03K3/38 ,  H04L29/08 ,  G06N10/00 ,  G06F15/76

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

公开(公告)号：US10769545B2

公开(公告)日：2020-09-08

申请号：US14734924

申请日：2015-06-09

Applicant: D-Wave Systems Inc.

Inventor： Mohammad H.S. Amin ,  Mark W. Johnson

IPC: G06F17/00 ,  G06N5/00 ,  G06N10/00

Abstract: A second problem Hamiltonian may replace a first problem Hamiltonian during evolution of an analog processor (e.g., quantum processor) during a first iteration in solving a first problem. This may be repeated during a second, or further successive iterations on the first problem, following re-initialization of the analog processor. An analog processor may evolve under a first non-monotonic evolution schedule during a first iteration, and second non-monotonic evolution schedule under second, or additional non-monotonic evolution schedule under even further iterations. A first graph and second graph may each be processed to extract final states versus a plurality of evolution schedules, and a determination made as to whether the first graph is isomorphic with respect to the second graph. An analog processor may evolve by decreasing a temperature of, and a set of quantum fluctuations, within the analog processor until the analog processor reaches a state preferred by a problem Hamiltonian.

公开(公告)号：US20200274050A1

公开(公告)日：2020-08-27

申请号：US16870537

申请日：2020-05-08

Applicant: D-WAVE SYSTEMS INC.

Inventor： Eric Ladizinsky ,  Jeremy P. Hilton ,  Byong Hyop Oh ,  Paul I. Bunyk

IPC: H01L39/24 ,  B82Y10/00 ,  H01L27/18 ,  H01L39/22 ,  H01L21/285 ,  H01L21/768 ,  H01L39/02 ,  H01L39/12

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

公开(公告)号：US20200210876A1

公开(公告)日：2020-07-02

申请号：US15753661

申请日：2016-08-18

Applicant: D-Wave Systems Inc.

Inventor： Jason Rolfe ,  Dmytro Korenkevych ,  Mani Ranjbar ,  Jack R. Raymond ,  William G. Macready

IPC: G06N10/00 ,  G06N3/08 ,  G06N5/04 ,  G06N20/00 ,  G06F17/18 ,  G06T1/20 ,  G06F15/80

Abstract: A computational system can include digital circuitry and analog circuitry, for instance a digital processor and a quantum processor. The quantum processor can operate as a sample generator providing samples. Samples can be employed by the digital processing in implementing various machine learning techniques. For example, the digital processor can operate as a restricted Boltzmann machine. The computational system can operate as a quantum-based deep belief network operating on a training data-set.

公开(公告)号：US20200160175A1

公开(公告)日：2020-05-21

申请号：US16682976

申请日：2019-11-13

Applicant: D-WAVE SYSTEMS INC.

Inventor： Arash Vahdat ,  Mostafa S. Ibrahim ,  William G. Macready

IPC: G06N3/08 ,  G06N3/04

Abstract: Fully-supervised semantic segmentation machine learning models are augmented by ancillary machine learning models which generate high-detail predictions from low-detail, weakly-supervised data. The combined model can be trained over both fully- and weakly-supervised data. Only the primary model is required for inference, post-training. The combined model can be made self-correcting during training by adjusting the ancillary model's output based on parameters learned over both the fully- and weakly-supervised data. The self-correction module may combine the output of the primary and ancillary models in various ways, including through linear combinations and via neural networks. The self-correction module and ancillary model may benefit from disclosed pre-training techniques.