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公开(公告)号：US11930721B2
公开(公告)日：2024-03-12
申请号：US16870537
申请日：2020-05-08
Applicant: D-WAVE SYSTEMS INC.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
IPC: H10N60/01 , B82Y10/00 , H01L21/285 , H01L21/768 , H10N60/10 , H10N60/12 , H10N60/80 , H10N60/85 , H10N69/00 , G06N10/00
CPC classification number: H10N60/0912 , B82Y10/00 , H01L21/2855 , H01L21/76877 , H01L21/76891 , H10N60/01 , H10N60/0156 , H10N60/10 , H10N60/12 , H10N60/805 , H10N60/855 , H10N69/00 , G06N10/00
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US10700256B2
公开(公告)日：2020-06-30
申请号：US15679963
申请日：2017-08-17
Applicant: D-WAVE SYSTEMS INC.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
IPC: H01L39/24 , H01L27/18 , H01L39/22 , H01L21/285 , H01L39/02 , H01L39/12 , B82Y10/00 , H01L21/768 , G06N10/00
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US20180033944A1
公开(公告)日：2018-02-01
申请号：US15679963
申请日：2017-08-17
Applicant: D-WAVE SYSTEMS INC.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
CPC classification number: H01L39/2493 , B82Y10/00 , G06N10/00 , H01L21/2855 , H01L21/76877 , H01L21/76891 , H01L27/18 , H01L39/025 , H01L39/125 , H01L39/22 , H01L39/223 , H01L39/24 , H01L39/2406
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US09768371B2
公开(公告)日：2017-09-19
申请号：US14383837
申请日：2013-03-07
Applicant: D-Wave Systems Inc.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
CPC classification number: H01L39/2493 , B82Y10/00 , G06N99/002 , H01L27/18 , H01L39/025 , H01L39/125 , H01L39/22 , H01L39/223 , H01L39/24 , H01L39/2406
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US20170098682A1
公开(公告)日：2017-04-06
申请号：US15289782
申请日：2016-10-10
Applicant: D-Wave Systems Inc.
Inventor： Eric Ladizinsky , Geordie Rose , Jeremy P. Hilton , Eugene Dantsker , Byong Hyop Oh
CPC classification number: H01L27/18 , B82Y10/00 , G06N99/002 , H01L28/24 , H01L39/025 , H01L39/223 , H01L39/2406 , H01L39/2493 , Y10S977/707 , Y10S977/723 , Y10S977/943
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
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Patent Agency Ranking
公开(公告)号：US10991755B2
公开(公告)日：2021-04-27
申请号：US16569221
申请日：2019-09-12
Applicant: D-WAVE SYSTEMS INC.
Inventor： Eric Ladizinsky , Geordie Rose , Jeremy P. Hilton , Eugene Dantsker , Byong Hyop Oh
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
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公开(公告)号：US20180308896A1
公开(公告)日：2018-10-25
申请号：US15956404
申请日：2018-04-18
Applicant: D-Wave Systems Inc.
Inventor： Eric Ladizinsky , Geordie Rose , Jeremy P. Hilton , Eugene Dantsker , Byong Hyop Oh
CPC classification number: H01L27/18 , B82Y10/00 , G06N10/00 , H01L28/24 , H01L39/025 , H01L39/223 , H01L39/2406 , H01L39/2493 , Y10S977/707 , Y10S977/723 , Y10S977/943
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
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公开(公告)号：US20200274050A1
公开(公告)日：2020-08-27
申请号：US16870537
申请日：2020-05-08
Applicant: D-WAVE SYSTEMS INC.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
IPC: H01L39/24 , B82Y10/00 , H01L27/18 , H01L39/22 , H01L21/285 , H01L21/768 , H01L39/02 , H01L39/12
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US09634224B2
公开(公告)日：2017-04-25
申请号：US14600962
申请日：2015-01-20
Applicant: D-Wave Systems Inc.
Inventor： Eric Ladizinsky , Nicolas Ladizinsky , Jason Yao , Byong Hyop Oh , Richard David Neufeld
CPC classification number: H01L39/2493 , H01L27/18 , H01L39/223
Abstract: In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.
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公开(公告)号：US20150236235A1
公开(公告)日：2015-08-20
申请号：US14600962
申请日：2015-01-20
Applicant: D-Wave Systems Inc.
Inventor： Eric Ladizinsky , Nicolas Ladizinsky , Jason Yao , Byong Hyop Oh , Richard David Neufeld
CPC classification number: H01L39/2493 , H01L27/18 , H01L39/223
Abstract: In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.
Abstract translation: 一方面，制造具有约瑟夫逊结的超导集成电路包括将氧或氮施加到由外部超导层形成的结构的至少一部分，以钝化去除外部超导层的部分留下的伪影（如果有的话）。 在另一方面，沉积第一超导层，在第一超导层上沉积第二超导层，在第一超导层上形成氧化物层，在氧化物层上沉积介电层，介电层的一部分 ，去除氧化物层的第一部分，形成第二氧化物部分代替氧化物层的第一部分，并且在介电层和第二氧化物部分上沉积第三超导层。
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