公开(公告)号：US20110299344A1

公开(公告)日：2011-12-08

申请号：US12796031

申请日：2010-06-08

申请人： Jack Z. Peng ,  David Fong

发明人： Jack Z. Peng ,  David Fong

IPC分类号： G11C7/00

CPC分类号： G11C17/16 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/003 ,  G11C17/18 ,  G11C2213/74 ,  G11C2213/79

摘要： A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines.

摘要翻译： 存储单元具有至少两个字线和至少两个位线。 该单元还具有连接到至少一个字线和一个位线的第一选择器件以及连接到至少一个字线和第一选择器件的栅极电容器元件。 该单元还具有与栅极电容器元件和第一选择器件串联连接的检测器件。 感测装置连接到至少两个位线。

公开(公告)号：US20110216572A1

公开(公告)日：2011-09-08

申请号：US13024231

申请日：2011-02-09

申请人： Jack Zezhong Peng ,  David Fong ,  Glen Arnold Rosendale

发明人： Jack Zezhong Peng ,  David Fong ,  Glen Arnold Rosendale

IPC分类号： G11C17/16

CPC分类号： G11C17/18

摘要： One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.

摘要翻译： 公开了一次性可编程（OTP）非易失性熔丝存储器单元，其不需要用于读取其数据内容的解码或寻址。 每个保险丝存储单元的内容在其输出端被锁存并且始终可用，并且可以用于例如代码存储存储器，串行配置存储器，以及作为用于ID（识别），修整和其他后期处理的单个保险丝位。 制造片上系统（SoC）定制需求。 还提供了用于设计测试等的临时数据存储的手段。在替代实施例中，在单个存储器单元中使用两个差分编程的熔丝，合并选择和编程电路。

公开(公告)号：US07464367B2

公开(公告)日：2008-12-09

申请号：US10619128

申请日：2003-07-14

申请人： Mark N. Wain ,  Dharma Shukla ,  Mayank Mehta ,  David Fong ,  Aditya Bhandarkar

发明人： Mark N. Wain ,  Dharma Shukla ,  Mayank Mehta ,  David Fong ,  Aditya Bhandarkar

IPC分类号： G06F9/44 ,  G06F3/00

CPC分类号： G06F8/34

摘要： The present invention enables a user to build user-interfaces and applications based on a policy that contains metadata. The user can build an application through the user-interface, in which the user-interface and the generated computer-executable instructions are consistent with the policy. A user-interface has a toolbox that indicates the discovered components and a design surface that displays applicable stages. The policy determines the stages, where each stage provides a grouping of components having related tasks. The user selects components from the toolbox so that the selected components are associated with the selected stages on the design surface. After the user has completed building an application, a representation of the application may be compiled in order to generate a set of computer-executable instructions. Moreover, the compiler is coupled to the policy so that the set of computer-executable instructions is consistent with the policy.

摘要翻译： 本发明使得用户能够基于包含元数据的策略构建用户界面和应用。 用户可以通过用户界面构建应用程序，用户界面和生成的计算机可执行指令与策略一致。 用户界面具有指示发现的组件的工具箱和显示适用阶段的设计曲面。 该策略确定阶段，每个阶段提供具有相关任务的组件分组。 用户从工具箱中选择组件，使所选择的组件与设计表面上的所选阶段相关联。 在用户完成构建应用程序之后，可以编译应用程序的表示，以便生成一组计算机可执行指令。 而且，编译器被耦合到策略，使得该组计算机可执行指令与该策略一致。

公开(公告)号：US20070230232A1

公开(公告)日：2007-10-04

申请号：US11759050

申请日：2007-06-06

申请人： David Fong ,  Jianguo Wang ,  Jack Peng ,  Harry Luan

发明人： David Fong ,  Jianguo Wang ,  Jack Peng ,  Harry Luan

IPC分类号： G11C17/00

CPC分类号： G11C7/08 ,  G11C7/18 ,  G11C16/28 ,  G11C2207/061 ,  G11C2207/065

摘要： Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

摘要翻译： 公开了减少存储晶体管的氧化物应力和提高可靠性的方法和装置。 存储晶体管栅极对读取信号的持续时间和频率显着降低。 在一些实施例中，在短的读取周期之后，只要后续读取尝试被引导到相同的存储器单元，存储器单元的内容被锁存和维持。 在这些实施例中，读周期只需要足够长的时间来锁存单元的存储器内容，并且只要随后的读取尝试针对相同的存储单元，将使用锁存值而不是重复读取处理。

公开(公告)号：US07277348B2

公开(公告)日：2007-10-02

申请号：US11356805

申请日：2006-02-17

申请人： Jack Zezhong Peng ,  David Fong ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshang Liu

发明人： Jack Zezhong Peng ,  David Fong ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshang Liu

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C2216/26

摘要： Memory cells including an SRAM and an OTP memory unit that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. The concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

摘要翻译： 存储单元包括SRAM和OTP存储器单元，其结合了两种技术的优点，并且可以通过标准CMOS制造制造而不需要额外的掩蔽。 概念和细节可以应用于需要存储器和/或采用其它制造技术的其他系统中并被应用。 除了其他优点之外，存储器单元的SRAM部分允许对单元进行无数次的编程，这在原型设计中是有用的。 OTP部分用于通过使用外部数据或已经存在于单元的SRAM部分中的数据来永久地编程存储器单元。 OTP单元保存的值也可以直接写入单元的SRAM部分。

公开(公告)号：US20070133334A1

公开(公告)日：2007-06-14

申请号：US11356805

申请日：2006-02-17

申请人： Jack Peng ,  David Fong ,  Harry Luan ,  Jianguo Wang ,  Zhongshang Liu

发明人： Jack Peng ,  David Fong ,  Harry Luan ,  Jianguo Wang ,  Zhongshang Liu

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C2216/26

摘要： Memory cells comprising an SRAM and an OTP memory unit are disclosed that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. Disclosed concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of disclosed memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

摘要翻译： 公开了包括SRAM和OTP存储器单元的存储器单元，其结合了这两种技术的优点，并且可以通过标准CMOS制造来制造而不需要额外的掩蔽。 公开的概念和细节可以应用于需要存储器和/或采用其它制造技术的其他系统中并被应用。 除了其他优点之外，所公开的存储单元的SRAM部分允许对单元进行无数次编程，这在例如原型设计期间是有用的。 OTP部分用于通过使用外部数据或已经存在于单元的SRAM部分中的数据来永久地编程存储器单元。 OTP单元保存的值也可以直接写入单元的SRAM部分。

公开(公告)号：US06856540B2

公开(公告)日：2005-02-15

申请号：US10448505

申请日：2003-05-30

申请人： Jack Zezhong Peng ,  David Fong

发明人： Jack Zezhong Peng ,  David Fong

IPC分类号： G11C17/12 ,  G11C11/34

CPC分类号： G11C17/16

摘要： A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+region in the substrate underlying the gate of the transistor.

摘要翻译： 公开了一种由位于列位线和行字线交叉点的晶体管构成的可编程存储单元。 晶体管的栅极由列位线形成，其栅极连接到行字线。 通过在列位线和行字线之间施加电压电位来编程存储器单元，以在晶体管的栅极下方的衬底中产生编程的n +区。

公开(公告)号：US20070153989A1

公开(公告)日：2007-07-05

申请号：US11324208

申请日：2005-12-30

申请人： David Howell ,  Sridhar Sundararaman ,  David Fong ,  Frank Seide

发明人： David Howell ,  Sridhar Sundararaman ,  David Fong ,  Frank Seide

IPC分类号： H04M11/00

CPC分类号： H04M3/5307 ,  H04M2201/405 ,  H04M2201/60 ,  H04M2203/253 ,  H04M2203/4509

摘要： Improved systems and methods are provided for transcribing audio files of voice mails sent over a unified messaging system. Customized grammars specific to a voice mail recipient are created and utilized to transcribe a received voice mail by comparing the audio file to commonly utilized words, names, acronyms, and phrases used by the recipient. Key elements are identified from the resulting text transcription to aid the recipient in processing received voice mails based on the significant content contained in the voice mail.

摘要翻译： 提供了改进的系统和方法，用于转录通过统一消息系统发送的语音邮件的音频文件。 通过将音频文件与收件人使用的常用词，名称，首字母缩略词和短语进行比较，创建和利用特定于语音邮件收件人的定制语法来转录接收到的语音邮件。 从所得到的文本转录中识别关键要素，以帮助接收者基于语音邮件中包含的重要内容来处理接收的语音邮件。

公开(公告)号：US20060259884A1

公开(公告)日：2006-11-16

申请号：US11125991

申请日：2005-05-10

申请人： David Fong ,  Zheng Zhang ,  Qi Chen

发明人： David Fong ,  Zheng Zhang ,  Qi Chen

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F17/00

CPC分类号： G06F17/5022

摘要： A method is provided for merging assertions in one input file with hardware description language (HDL) code in another input file to produce an HDL output file. One embodiment, among others, comprises the steps of: copying an assertion identified by an assertion identifier from the first input file; locating a matching assertion identifier within a section of the second input file; and merging the assertion with the section of the second input file to produce a section in the HDL output file.

摘要翻译： 提供一种用于将一个输入文件中的断言与另一个输入文件中的硬件描述语言（HDL）代码合并以产生HDL输出文件的方法。 一个实施例包括以下步骤：从第一输入文件复制由断言标识符识别的断言; 在所述第二输入文件的一部分内定位匹配的断言标识符; 并将断言与第二个输入文件的部分合并，以产生HDL输出文件中的一个部分。

公开(公告)号：US20050010427A1

公开(公告)日：2005-01-13

申请号：US10617904

申请日：2003-07-11

申请人： Aditya Bhandarkar ,  David Fong ,  Eddie Fusaro ,  Mayank Mehta ,  Anand Ramanathan ,  Dharma Shukla ,  Kumarswamy Valegerepura ,  Mark Wain ,  Muralidhara Chilayurl

发明人： Aditya Bhandarkar ,  David Fong ,  Eddie Fusaro ,  Mayank Mehta ,  Anand Ramanathan ,  Dharma Shukla ,  Kumarswamy Valegerepura ,  Mark Wain ,  Muralidhara Chilayurl

IPC分类号： G06Q10/00 ,  G06F17/60

CPC分类号： G06Q10/06 ,  G06Q10/103

摘要： Partner management systems and methods are disclosed. A designer designs a business process that provides selection criteria for selecting business partners. The business process is compiled and executed by a business process execution engine. During the execution of the business process, the business process execution engine uses the selection criteria to select business partners. The identification of business partners and attributes of the business partners may be modified without modifying the business process.

摘要翻译： 披露合作伙伴管理系统和方法。 设计师设计一个业务流程，为选择业务伙伴提供选择标准。 业务流程由业务流程执行引擎编译和执行。 在业务流程执行期间，业务流程执行引擎使用选择标准来选择业务伙伴。 业务合作伙伴的身份识别和业务伙伴的属性可能会被修改，而无需修改业务流程。