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    Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit
    1.
    发明申请
    Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit 有权
    存储单元包括OTP非易失性存储单元和SRAM单元

    公开(公告)号：US20070133334A1

    公开(公告)日：2007-06-14

    申请号：US11356805

    申请日：2006-02-17

    申请人： Jack Peng ,  David Fong ,  Harry Luan ,  Jianguo Wang ,  Zhongshang Liu

    发明人： Jack Peng ,  David Fong ,  Harry Luan ,  Jianguo Wang ,  Zhongshang Liu

    IPC分类号： G11C17/18

    CPC分类号： G11C17/16 ,  G11C2216/26

    摘要： Memory cells comprising an SRAM and an OTP memory unit are disclosed that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. Disclosed concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of disclosed memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

    摘要翻译： 公开了包括SRAM和OTP存储器单元的存储器单元，其结合了这两种技术的优点，并且可以通过标准CMOS制造来制造而不需要额外的掩蔽。 公开的概念和细节可以应用于需要存储器和/或采用其它制造技术的其他系统中并被应用。 除了其他优点之外，所公开的存储单元的SRAM部分允许对单元进行无数次编程，这在例如原型设计期间是有用的。 OTP部分用于通过使用外部数据或已经存在于单元的SRAM部分中的数据来永久地编程存储器单元。 OTP单元保存的值也可以直接写入单元的SRAM部分。

    MEMORY TRANSISTOR GATE OXIDE STRESS RELEASE AND IMPROVED RELIABILITY
    2.
    发明申请
    MEMORY TRANSISTOR GATE OXIDE STRESS RELEASE AND IMPROVED RELIABILITY 有权
    内存晶闸管氧化物应力释放和改进的可靠性

    公开(公告)号：US20070230232A1

    公开(公告)日：2007-10-04

    申请号：US11759050

    申请日：2007-06-06

    申请人： David Fong ,  Jianguo Wang ,  Jack Peng ,  Harry Luan

    发明人： David Fong ,  Jianguo Wang ,  Jack Peng ,  Harry Luan

    IPC分类号： G11C17/00

    CPC分类号： G11C7/08 ,  G11C7/18 ,  G11C16/28 ,  G11C2207/061 ,  G11C2207/065

    摘要： Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

    摘要翻译： 公开了减少存储晶体管的氧化物应力和提高可靠性的方法和装置。 存储晶体管栅极对读取信号的持续时间和频率显着降低。 在一些实施例中，在短的读取周期之后，只要后续读取尝试被引导到相同的存储器单元，存储器单元的内容被锁存和维持。 在这些实施例中，读周期只需要足够长的时间来锁存单元的存储器内容，并且只要随后的读取尝试针对相同的存储单元，将使用锁存值而不是重复读取处理。

    Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit
    4.
    发明授权
    Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit 有权
    存储单元包括OTP非易失性存储单元和SRAM单元

    公开(公告)号：US07277348B2

    公开(公告)日：2007-10-02

    申请号：US11356805

    申请日：2006-02-17

    申请人： Jack Zezhong Peng ,  David Fong ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshang Liu

    发明人： Jack Zezhong Peng ,  David Fong ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshang Liu

    IPC分类号： G11C17/18

    CPC分类号： G11C17/16 ,  G11C2216/26

    摘要： Memory cells including an SRAM and an OTP memory unit that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. The concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

    摘要翻译： 存储单元包括SRAM和OTP存储器单元，其结合了两种技术的优点，并且可以通过标准CMOS制造制造而不需要额外的掩蔽。 概念和细节可以应用于需要存储器和/或采用其它制造技术的其他系统中并被应用。 除了其他优点之外，存储器单元的SRAM部分允许对单元进行无数次的编程，这在原型设计中是有用的。 OTP部分用于通过使用外部数据或已经存在于单元的SRAM部分中的数据来永久地编程存储器单元。 OTP单元保存的值也可以直接写入单元的SRAM部分。

    Field programmable gate array logic unit and its cluster
    6.
    发明申请
    Field programmable gate array logic unit and its cluster 审中-公开

    公开(公告)号：US20050275427A1

    公开(公告)日：2005-12-15

    申请号：US10916232

    申请日：2004-08-11

    申请人： Man Wang ,  Guy Schlacter ,  David Fong ,  Jianguo Wang ,  Jack Peng

    发明人： Man Wang ,  Guy Schlacter ,  David Fong ,  Jianguo Wang ,  Jack Peng

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17728

    摘要： The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.

    Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage
    8.
    发明授权
    Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage 有权
    测试使用击穿电压的半导体存储单元的薄氧化物的方法

    公开(公告)号：US06791891B1

    公开(公告)日：2004-09-14

    申请号：US10406406

    申请日：2003-04-02

    申请人： Jack Zezhong Peng ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshan Liu ,  David Fong ,  Fei Ye

    发明人： Jack Zezhong Peng ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshan Liu ,  David Fong ,  Fei Ye

    IPC分类号： G11C700

    CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2029/5002

    摘要： A method of testing a memory cell is disclosed. The memory cell has a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, which is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. In order to ensure that the gate oxide underlying the data storage elements are of sufficient quality for programming, the memory cells of a memory array may be tested by applying a voltage across the gate oxide of the data storage element and measuring the current flow. Resultant current flow outside of a predetermined range indicates a defective memory cell.

    摘要翻译： 公开了一种测试存储单元的方法。 存储单元具有围绕诸如栅极氧化物的超薄电介质构成的数据存储元件，其用于通过将超薄电介质压制成击穿（软或硬击穿）来存储信息，以设置泄漏电流水平 存储单元。 为了确保数据存储元件下面的栅极氧化物具有足够的编程质量，可以通过在数据存储元件的栅极氧化物上施加电压并测量电流来测试存储器阵列的存储单元。 在预定范围之外的所得电流表示有缺陷的存储单元。

    Memory transistor gate oxide stress release and improved reliability
    9.
    发明授权
    Memory transistor gate oxide stress release and improved reliability 有权
    记忆晶体管栅氧化层应力释放和可靠性提高

    公开(公告)号：US07471541B2

    公开(公告)日：2008-12-30

    申请号：US11759050

    申请日：2007-06-06

    申请人： David Fong ,  Jianguo Wang ,  Jack Zezhong Peng ,  Harry Shengwen Luan

    发明人： David Fong ,  Jianguo Wang ,  Jack Zezhong Peng ,  Harry Shengwen Luan

    IPC分类号： G11C7/00

    CPC分类号： G11C7/08 ,  G11C7/18 ,  G11C16/28 ,  G11C2207/061 ,  G11C2207/065

    摘要： Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

    摘要翻译： 公开了减少存储晶体管的氧化物应力和提高可靠性的方法和装置。 存储晶体管栅极对读取信号的持续时间和频率显着降低。 在一些实施例中，在短的读取周期之后，只要后续读取尝试被引导到相同的存储器单元，存储器单元的内容被锁存和维持。 在这些实施例中，读周期只需要足够长的时间来锁存单元的存储器内容，并且只要随后的读取尝试针对相同的存储单元，将使用锁存值而不是重复读取处理。

    Memory transistor gate oxide stress release and improved reliability
    10.
    发明授权
    Memory transistor gate oxide stress release and improved reliability 有权
    记忆晶体管栅氧化层应力释放和可靠性提高

    公开(公告)号：US07269047B1

    公开(公告)日：2007-09-11

    申请号：US11368576

    申请日：2006-03-06

    申请人： David Fong ,  Jianguo Wang ,  Jack Zezhong Peng ,  Harry Shengwen Luan

    发明人： David Fong ,  Jianguo Wang ,  Jack Zezhong Peng ,  Harry Shengwen Luan

    IPC分类号： G11C17/00

    CPC分类号： G11C7/08 ,  G11C7/18 ,  G11C16/28 ,  G11C2207/061 ,  G11C2207/065

    摘要： Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

    摘要翻译： 公开了减少存储晶体管的氧化物应力和提高可靠性的方法和装置。 存储晶体管栅极对读取信号的持续时间和频率显着降低。 在一些实施例中，在短的读取周期之后，只要后续读取尝试被引导到相同的存储器单元，存储器单元的内容被锁存和维持。 在这些实施例中，读周期只需要足够长的时间来锁存单元的存储器内容，并且只要随后的读取尝试针对相同的存储单元，将使用锁存值而不是重复读取处理。