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    Merging a hardware design language source file with a separate assertion file
    1.
    发明申请
    Merging a hardware design language source file with a separate assertion file 有权
    将硬件设计语言源文件与单独的断言文件合并

    公开(公告)号：US20060259884A1

    公开(公告)日：2006-11-16

    申请号：US11125991

    申请日：2005-05-10

    申请人： David Fong ,  Zheng Zhang ,  Qi Chen

    发明人： David Fong ,  Zheng Zhang ,  Qi Chen

    IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F17/00

    CPC分类号： G06F17/5022

    摘要： A method is provided for merging assertions in one input file with hardware description language (HDL) code in another input file to produce an HDL output file. One embodiment, among others, comprises the steps of: copying an assertion identified by an assertion identifier from the first input file; locating a matching assertion identifier within a section of the second input file; and merging the assertion with the section of the second input file to produce a section in the HDL output file.

    摘要翻译： 提供一种用于将一个输入文件中的断言与另一个输入文件中的硬件描述语言（HDL）代码合并以产生HDL输出文件的方法。 一个实施例包括以下步骤：从第一输入文件复制由断言标识符识别的断言; 在所述第二输入文件的一部分内定位匹配的断言标识符; 并将断言与第二个输入文件的部分合并，以产生HDL输出文件中的一个部分。

    System and method for generating assertions using waveforms
    2.
    发明申请
    System and method for generating assertions using waveforms 审中-公开
    使用波形生成断言的系统和方法

    公开(公告)号：US20060190882A1

    公开(公告)日：2006-08-24

    申请号：US11050212

    申请日：2005-02-03

    申请人： David Fong ,  Zheng Zhang ,  Qi Chen

    发明人： David Fong ,  Zheng Zhang ,  Qi Chen

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Systems and methods for generating a Hardware Design Language (HDL) assertion from a waveform diagram are disclosed. One method comprises: identifying a timing relationship between first and second signals in the diagram; and generating an HDL assertion corresponding to the relationship. The relationship comprises a portion of the first signal, a portion of the second signal, and an interval between the portions. Another method comprises: identifying a combinatorial relationship between two input signals and an output signal in the diagram; and generating an HDL assertion corresponding to the relationship. One system comprises logic for performing the steps of: receiving a plurality of signal descriptions, each describing one of a plurality of signals; receiving a description of a timing or combinatorial relationship between at least two of the plurality of signals; generating a waveform diagram including a representation of the relationship; and generating an HDL assertion corresponding to the relationship.

    摘要翻译： 公开了从波形图生成硬件设计语言（HDL）断言的系统和方法。 一种方法包括：识别图中第一和第二信号之间的定时关系; 以及生成对应于该关系的HDL断言。 该关系包括第一信号的一部分，第二信号的一部分以及部分之间的间隔。 另一种方法包括：识别图中两个输入信号与输出信号之间的组合关系; 以及生成对应于该关系的HDL断言。 一个系统包括用于执行以下步骤的逻辑：接收多个信号描述，每个信号描述描述多个信号中的一个; 接收对所述多个信号中的至少两个信号之间的定时或组合关系的描述; 生成包括所述关系的表示的波形图; 以及生成对应于该关系的HDL断言。

    Personalized user specific grammars
    3.
    发明申请
    Personalized user specific grammars 失效
    个性化用户特定语法

    公开(公告)号：US20070153989A1

    公开(公告)日：2007-07-05

    申请号：US11324208

    申请日：2005-12-30

    申请人： David Howell ,  Sridhar Sundararaman ,  David Fong ,  Frank Seide

    发明人： David Howell ,  Sridhar Sundararaman ,  David Fong ,  Frank Seide

    IPC分类号： H04M11/00

    CPC分类号： H04M3/5307 ,  H04M2201/405 ,  H04M2201/60 ,  H04M2203/253 ,  H04M2203/4509

    摘要： Improved systems and methods are provided for transcribing audio files of voice mails sent over a unified messaging system. Customized grammars specific to a voice mail recipient are created and utilized to transcribe a received voice mail by comparing the audio file to commonly utilized words, names, acronyms, and phrases used by the recipient. Key elements are identified from the resulting text transcription to aid the recipient in processing received voice mails based on the significant content contained in the voice mail.

    摘要翻译： 提供了改进的系统和方法，用于转录通过统一消息系统发送的语音邮件的音频文件。 通过将音频文件与收件人使用的常用词，名称，首字母缩略词和短语进行比较，创建和利用特定于语音邮件收件人的定制语法来转录接收到的语音邮件。 从所得到的文本转录中识别关键要素，以帮助接收者基于语音邮件中包含的重要内容来处理接收的语音邮件。

    Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage
    5.
    发明授权
    Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage 有权
    测试使用击穿电压的半导体存储单元的薄氧化物的方法

    公开(公告)号：US06791891B1

    公开(公告)日：2004-09-14

    申请号：US10406406

    申请日：2003-04-02

    申请人： Jack Zezhong Peng ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshan Liu ,  David Fong ,  Fei Ye

    发明人： Jack Zezhong Peng ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshan Liu ,  David Fong ,  Fei Ye

    IPC分类号： G11C700

    CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2029/5002

    摘要： A method of testing a memory cell is disclosed. The memory cell has a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, which is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. In order to ensure that the gate oxide underlying the data storage elements are of sufficient quality for programming, the memory cells of a memory array may be tested by applying a voltage across the gate oxide of the data storage element and measuring the current flow. Resultant current flow outside of a predetermined range indicates a defective memory cell.

    摘要翻译： 公开了一种测试存储单元的方法。 存储单元具有围绕诸如栅极氧化物的超薄电介质构成的数据存储元件，其用于通过将超薄电介质压制成击穿（软或硬击穿）来存储信息，以设置泄漏电流水平 存储单元。 为了确保数据存储元件下面的栅极氧化物具有足够的编程质量，可以通过在数据存储元件的栅极氧化物上施加电压并测量电流来测试存储器阵列的存储单元。 在预定范围之外的所得电流表示有缺陷的存储单元。

    Methods and systems for repairing an integrated circuit device
    6.
    发明申请
    Methods and systems for repairing an integrated circuit device 有权
    用于修复集成电路设备的方法和系统

    公开(公告)号：US20070226556A1

    公开(公告)日：2007-09-27

    申请号：US11389710

    申请日：2006-03-27

    申请人： David Fong ,  Gang Miao

    发明人： David Fong ,  Gang Miao

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318516 ,  G01R31/31704

    摘要： Provided are systems for repairing an integrated circuit device. The systems include detection logic configured to locate a defective portion of an integrated circuit device, a supplemental integrated circuit component configured to functionally replace the defective portion, and logic configured to identify an interface location. Also provided are methods for repairing an integrated circuit device. The methods include the steps of: identifying a defective portion of an integrated circuit device; disconnecting existing circuit components; and incorporating a supplemental integrated circuit component with the integrated circuit device.

    摘要翻译： 提供了用于修复集成电路器件的系统。 所述系统包括被配置为定位集成电路设备的缺陷部分的检测逻辑，被配置为功能地替换缺陷部分的补充集成电路部件以及被配置为识别接口位置的逻辑。 还提供了用于修复集成电路装置的方法。 所述方法包括以下步骤：识别集成电路器件的缺陷部分; 断开现有电路部件; 并将集成电路器件与补充集成电路器件相结合。

    Field programmable gate array logic unit and its cluster
    9.
    发明申请
    Field programmable gate array logic unit and its cluster 审中-公开

    公开(公告)号：US20050275427A1

    公开(公告)日：2005-12-15

    申请号：US10916232

    申请日：2004-08-11

    申请人： Man Wang ,  Guy Schlacter ,  David Fong ,  Jianguo Wang ,  Jack Peng

    发明人： Man Wang ,  Guy Schlacter ,  David Fong ,  Jianguo Wang ,  Jack Peng

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17728

    摘要： The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.

    High density semiconductor memory cell and memory array using a single transistor
    10.
    发明授权
    High density semiconductor memory cell and memory array using a single transistor 有权
    使用单晶体管的高密度半导体存储单元和存储器阵列

    公开(公告)号：US06777757B2

    公开(公告)日：2004-08-17

    申请号：US10133704

    申请日：2002-04-26

    申请人： Jack Zezhong Peng ,  David Fong

    发明人： Jack Zezhong Peng ,  David Fong

    IPC分类号： H01L2994

    CPC分类号： G11C17/16

    摘要： A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor.

    摘要翻译： 公开了一种由位于列位线和行字线交叉点的晶体管构成的可编程存储单元。 晶体管的栅极由列位线形成，其栅极连接到行字线。 通过在列位线和行字线之间施加电压电位来编程存储器单元，以在晶体管的栅极下方的衬底中产生编程的n +区。