公开(公告)号：US20090021264A1

公开(公告)日：2009-01-22

申请号：US11780505

申请日：2007-07-20

Applicant: Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

Inventor： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

IPC: G01R31/02 ,  G06F11/00

CPC classification number: G01R31/2815 ,  G01R31/304 ,  G11C29/02 ,  G11C29/022 ,  G11C29/56 ,  G11C2029/5602

Abstract: The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.

Abstract translation: 本发明通过计算由诸如偶极天线的装置收集的辐射场的频率内容来评估存储器（DIMM）强度。 辐射场由加速电荷产生，这是压摆率或DIMM强度的函数。 辐射功率与驱动位的频率成正比。 通过将辐射场与近场或存储场分离，DIMM强度内容与其他功能性DIMM问题（例如tRCD延迟，刷新周期，寻址模式等）隔离。通过检查辐射功率，现有技术的缺点 ，例如通过探测DIMM的触点。

公开(公告)号：US07474117B1

公开(公告)日：2009-01-06

申请号：US12127165

申请日：2008-05-27

Applicant: Justin P. Bandholz ,  Moises Cases ,  Bradley D. Herman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Thomas D. Pahel ,  Pravin S. Patel ,  Nam H. Pham ,  Christopher C. West

Inventor： Justin P. Bandholz ,  Moises Cases ,  Bradley D. Herman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Thomas D. Pahel ,  Pravin S. Patel ,  Nam H. Pham ,  Christopher C. West

IPC: H03K17/16

CPC classification number: G06F13/4072

Abstract: A method of transmitting a signal on a bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupled in series with the non-inverting buffer circuit to provide AC coupling to the USB bus and to allow fast signal edges through the circuit. The booster circuit is arranged to improve signal quality over a USB bus to allow additional USB devices and longer USB busses to be utilized.

Abstract translation: 一种在双向通用串行总线（“USB”）电路上传输信号以提升USB总线上的信号的方法。 电路包括耦合到第二级反相缓冲器以形成非反相缓冲电路的第一级反相缓冲器。 高通滤波器与非反相缓冲电路串联耦合以提供与USB总线的AC耦合并允许通过电路的快速信号边缘。 升压电路被设置为通过USB总线提高信号质量，以允许使用附加的USB设备和更长的USB总线。

公开(公告)号：US20090007048A1

公开(公告)日：2009-01-01

申请号：US12203335

申请日：2008-09-03

Applicant: MOISES CASES ,  Martin J. Crippen ,  Daniel N. de Araujo ,  Bradley D. Herman ,  Erdem Matoglu ,  William R. Milani ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

Inventor： MOISES CASES ,  Martin J. Crippen ,  Daniel N. de Araujo ,  Bradley D. Herman ,  Erdem Matoglu ,  William R. Milani ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

IPC: G06F17/50

CPC classification number: H01R25/006

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory module system and DIMM connector is provided. A DIMM connector includes a plurality of DIMM sockets for receiving a corresponding plurality of DIMMs in a radially oriented, angularly spaced orientation. The DIMM sockets are connected in parallel at a memory module junction so that socket terminals of each DIMM socket are joined to the same relative terminal of all the other DIMM sockets along electronic pathways of substantially equal length. A memory controller selectively communicates with the DIMMs via the DIMM junction. By virtue of the improved topology, impedance within the DIMM connector may be better matched to minimize reflections and improve signal quality.

Abstract translation: 提供了体现在用于设计，制造和/或测试存储器模块系统和DIMM连接器的机器可读存储介质中的设计结构。 DIMM连接器包括多个DIMM插座，用于以径向定向的，有角度间隔的方向接收相应的多个DIMM。 DIMM插槽在存储器模块连接处并联连接，使得每个DIMM插座的插座端子沿着基本相等长度的电子路径连接到所有其他DIMM插槽的相同相对端子。 存储器控制器经由DIMM连接器选择性地与DIMM通信。 凭借改进的拓扑结构，可以更好地匹配DIMM连接器内的阻抗以最小化反射并提高信号质量。

公开(公告)号：US07443180B2

公开(公告)日：2008-10-28

申请号：US11567449

申请日：2006-12-06

Applicant: Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

Inventor： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R31/31723 ,  G01R31/2884 ,  G01R31/31926

Abstract: The invention is directed to an on-chip probing apparatus. In accordance with an embodiment of the present invention, the on-chip probing apparatus includes: a plurality of switches on a chip; a plurality of externally accessible probe points on the chip; and a multiplexer for controlling the plurality of switches to selectively couple an output signal of the chip to one of the plurality of probe points.

Abstract translation: 本发明涉及片上探测装置。 根据本发明的实施例，片上探测装置包括：芯片上的多个开关; 芯片上的多个外部可访问的探针点; 以及多路复用器，用于控制所述多个开关以选择性地将所述芯片的输出信号耦合到所述多个探针点中的一个。

公开(公告)号：US20080155149A1

公开(公告)日：2008-06-26

申请号：US11613363

申请日：2006-12-20

Applicant: Daniel N. de Araujo ,  Moises Cases ,  Erdem Matoglu ,  Nam H. Pham

Inventor： Daniel N. de Araujo ,  Moises Cases ,  Erdem Matoglu ,  Nam H. Pham

IPC: G06F13/16

CPC classification number: G06F11/2007

Abstract: The present invention is directed to a multi-path redundant architecture for fault tolerant fully buffered dual inline memory modules (FB-DIMMs). The architecture includes: a FB-DIMM channel including a plurality of DIMM modules and a memory controller; a bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a first connection order; and a redundant bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a second connection order

Abstract translation: 本发明涉及用于容错全缓冲双列直插式存储器模块（FB-DIMM）的多路径冗余架构。 该架构包括：包括多个DIMM模块的FB-DIMM通道和存储器控制器; 用于以第一连接顺序耦合存储器控制器和FB-DIMM通道的多个DIMM模块的双向串行存储器总线; 以及用于以第二连接顺序耦合存储器控制器和FB-DIMM通道的多个DIMM模块的冗余双向串行存储器总线