公开(公告)号：US08289101B2

公开(公告)日：2012-10-16

申请号：US11737196

申请日：2007-04-19

申请人： Justin P. Bandholz ,  Moises Cases ,  Robert J. Christopher ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

发明人： Justin P. Bandholz ,  Moises Cases ,  Robert J. Christopher ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

IPC分类号： H03H7/38

CPC分类号： H05K1/0237 ,  H04L25/028 ,  H04L25/0288 ,  H04L25/03343 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/1006

摘要： Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line.

摘要翻译： 本发明的实施例解决了PCB设计中的通孔结构利用方面的技术缺陷，并且提供了一种用于PCB中经由短线和连接器的阻抗不连续修复的新颖且非显而易见的方法，系统和计算机程序产品。 在一个实施例中，可以提供PCB中阻抗不连续修复的方法。 该方法可以包括配置预失真滤波器以消除由具有通孔短路或连接器之一的传输线引起的电信号中的阻抗不连续性。 该方法还可以包括在通过传输线路传输电信号之前对电信号进行预失真滤波。 最后，该方法可以包括通过传输线传输预失真滤波的电信号。

公开(公告)号：US20120249162A1

公开(公告)日：2012-10-04

申请号：US13524213

申请日：2012-06-15

申请人： Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Terence Rodrigues

发明人： Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Terence Rodrigues

IPC分类号： G01R27/02 ,  G01R35/00

CPC分类号： G01R31/2896

摘要： A method for altering an impedance of a conductive pathway on a microelectronic package includes applying a magnetic field to the conductive pathway. The microelectronic package may be, for example, a printed circuit board. The method also includes controlling a magnitude of the magnetic field at the conductive pathway for altering the impedance of the conductive pathway. The magnetic field may be applied by, for example, an electromagnet or a permanent magnet. A magnetic field may also be applied for simulating crosstalk effects on a conductive pathway.

摘要翻译： 用于改变微电子封装上的导电路径的阻抗的方法包括向导电路径施加磁场。 微电子封装可以是例如印刷电路板。 该方法还包括控制导电路径处的磁场的大小以改变导电路径的阻抗。 磁场可以由例如电磁体或永久磁铁施加。 也可以应用磁场来模拟对导电路径的串扰效应。

公开(公告)号：US20090107705A1

公开(公告)日：2009-04-30

申请号：US11924416

申请日：2007-10-25

申请人： Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

发明人： Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

IPC分类号： H05K3/00 ,  H05K1/03

CPC分类号： H05K1/024 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T156/1013

摘要： Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.

摘要翻译： 降低高速数字系统噪声耦合的方法和系统。 示例性实施例包括一种方法，包括将多个高速信号迹线蚀刻到芯绝缘层上，在多个高速信号迹线的相应侧上形成沟槽，从而去除与多个高速信号迹线相邻的绝缘材料，并形成 具有剩余绝缘材料的基座，多个高速信号迹线设置在剩余绝缘材料上并耦合到剩余的绝缘材料上，将高速信号迹线上的预预处理材料耦合，去除与沟槽相邻的预浸料， 将材料与高速信号迹线对准，并且将芯层加热并压制到预浸层，以及将预浸层加热和压制到芯绝缘层。

公开(公告)号：US20090106976A1

公开(公告)日：2009-04-30

申请号：US12174810

申请日：2008-07-17

申请人： Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

发明人： Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

IPC分类号： H05K3/02 ,  B29C53/00

CPC分类号： H05K1/024 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T156/1013

摘要： Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.

摘要翻译： 降低高速数字系统噪声耦合的方法和系统。 示例性实施例包括一种方法，包括将多个高速信号迹线蚀刻到芯绝缘层上，在多个高速信号迹线的相应侧上形成沟槽，从而去除与多个高速信号迹线相邻的绝缘材料，并形成 具有剩余绝缘材料的基座，多个高速信号迹线设置在剩余绝缘材料上并耦合到剩余的绝缘材料上，将高速信号迹线上的预预处理材料耦合，去除与沟槽相邻的预浸料， 将材料与高速信号迹线对准，并且将芯层加热并压制到预浸层，以及将预浸层加热和压制到芯绝缘层。

公开(公告)号：US20070178289A1

公开(公告)日：2007-08-02

申请号：US11340907

申请日：2006-01-27

申请人： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Pravin Patel ,  Nam H. Pham ,  Joffre A. Ratcliffe

发明人： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Pravin Patel ,  Nam H. Pham ,  Joffre A. Ratcliffe

IPC分类号： B32B3/00

CPC分类号： B32B17/04 ,  H05K1/0248 ,  H05K1/025 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09227 ,  Y10T428/24917

摘要： An electronic system includes a circuit board formed from a composite material. The composite material includes fibers embedded within a substrate and the fibers are oriented substantially orthogonal to one another. A plurality of traces are formed on the board, and the plurality of traces are oriented relative to at least one of the fibers at an angle between about 17.5° and about 27.5° or between about 20.0° and about 25.0°. A pair of the traces are oriented substantially orthogonal to one another, and a pair of the traces are oriented relative to one another at an angle of about 45.0°. The fibers are fiberglass, and the substrate is an epoxy resin. The fibers have a different dielectric constant than the substrate.

摘要翻译： 电子系统包括由复合材料形成的电路板。 复合材料包括嵌入基片内的纤维，纤维彼此基本正交。 在板上形成多个迹线，并且多个迹线相对于至少一个光纤以约17.5°至约27.5°之间的角度或约20.0°至约25.0°的角度定向。 一对迹线基本上彼此正交地定向，并且一对迹线以大约45.0°的角度相对于彼此定向。 纤维是玻璃纤维，基材是环氧树脂。 纤维的介电常数不同于基材。

公开(公告)号：US07956688B2

公开(公告)日：2011-06-07

申请号：US12574923

申请日：2009-10-07

申请人： Rubina F. Ahmed ,  Bradley D. Herrman ,  Pravin Patel ,  Peter R. Seidel

发明人： Rubina F. Ahmed ,  Bradley D. Herrman ,  Pravin Patel ,  Peter R. Seidel

IPC分类号： H03F3/45 ,  H03K19/094

CPC分类号： H04L25/0274 ,  H04L25/0284

摘要： Embodiments of the invention include a common mode cancellation circuit and method for correcting signal skew in a differential circuit. According to one embodiment, an op amp circuit is used to correct the mismatch between transmission line lengths in the differential circuit. The CMCC can be embodied as an ASIC and added on to an existing differential signaling systems to correct and compensate for board wiring skew or other causes of phase misalignment. The result is restoration of the cross-over intersection of the plus and minus signals of the differential pair closer to the common voltage level point, as if the signals had been in phase.

摘要翻译： 本发明的实施例包括用于校正差分电路中的信号偏移的共模消除电路和方法。 根据一个实施例，使用运算放大器电路来校正差分电路中的传输线路长度之间的失配。 CMCC可以实现为ASIC，并添加到现有的差分信号系统上，以纠正和补偿电路板布线偏移或相位未对准的其他原因。 结果是恢复差分对的正负信号与公共电压电平点的交叉交叉，好像信号是同相的。

公开(公告)号：US20100231209A1

公开(公告)日：2010-09-16

申请号：US12402806

申请日：2009-03-12

申请人： Rubina F. Ahmed ,  Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Peter R. Seidel

发明人： Rubina F. Ahmed ,  Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Peter R. Seidel

IPC分类号： G01R31/00

CPC分类号： G01R31/2806 ,  G01R15/183

摘要： Testing an electrical component, the component including a printed circuit board (‘PCB’) with a number of traces, the traces organized in pairs with each trace of a pair carrying current in opposite directions and separated from one another by a substrate layer of the PCB, where testing of the electrical component includes: dynamically and iteratively until a present impedance for a pair of traces of the component is greater than a predetermined threshold impedance: increasing, by an impedance varying device at the behest of a testing device, magnetic field strength of a magnetic field applied to the pair of traces by the impedance varying device, including increasing the present impedance of the pair of traces; measuring, by the testing device, one or more operating parameters; and recording, by the testing device, the measurements of the operating parameters.

摘要翻译： 测试电气部件，该部件包括具有多个迹线的印刷电路板（“PCB”），该迹线与成对的每个迹线成对地沿着相反的方向承载电流，并且彼此分离由基底层 PCB，其中电气部件的测试包括：动态地和迭代地，直到组件的一对迹线的当前阻抗大于预定阈值阻抗：通过测试装置的阻抗改变装置增加磁场 通过阻抗变化装置施加到该对迹线的磁场的强度，包括增加该对迹线的当前阻抗; 由所述测试装置测量一个或多个操作参数; 并由测试装置记录操作参数的测量值。

公开(公告)号：US07533458B1

公开(公告)日：2009-05-19

申请号：US12174810

申请日：2008-07-17

申请人： Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

发明人： Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

IPC分类号： H05K3/36

CPC分类号： H05K1/024 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T156/1013

摘要： Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.

摘要翻译： 降低高速数字系统噪声耦合的方法和系统。 示例性实施例包括一种方法，包括将多个高速信号迹线蚀刻到芯绝缘层上，在多个高速信号迹线的相应侧上形成沟槽，从而去除与多个高速信号迹线相邻的绝缘材料，并形成 具有剩余绝缘材料的基座，多个高速信号迹线设置在剩余绝缘材料上并耦合到剩余的绝缘材料上，将高速信号迹线上的预预处理材料耦合，去除与沟槽相邻的预浸料， 将材料与高速信号迹线对准，并且将芯层加热并压制到预浸层，以及将预浸层加热和压制到芯绝缘层。

公开(公告)号：US20080112503A1

公开(公告)日：2008-05-15

申请号：US11560257

申请日：2006-11-15

申请人： Daniel N. De Araujo ,  Moises Cases ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

发明人： Daniel N. De Araujo ,  Moises Cases ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

IPC分类号： H04L25/03

CPC分类号： H04L25/0264 ,  H04L25/0286

摘要： An apparatus, system, and method are disclosed for dynamic phase equalization in a communication channel. A transmitter history module stores a plurality of bits from a data stream that is transmitted through the communication channel. A transmitter detection module detects a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value. A driver module transmits the data stream by driving the communication channel. A transition module pre-drives the communication channel to the second voltage of the transition bit during a bit time interval of the pre-transition bit.

摘要翻译： 公开了用于通信信道中的动态相位均衡的装置，系统和方法。 发射机历史模块从通过通信信道发送的数据流存储多个比特。 发射机检测模块检测在数据流中前面的第一值的前转换比特的第一值的至少一个比特，然后跟随具有第二值的转换比特。 驾驶员模块通过驱动通信信道来发送数据流。 转换模块在预转换位的位时间间隔期间将通信通道预驱动到转换位的第二电压。

公开(公告)号：US09338881B2

公开(公告)日：2016-05-10

申请号：US13531959

申请日：2012-06-25

申请人： Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Nam H. Pham ,  Terence Rodrigues

发明人： Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Nam H. Pham ,  Terence Rodrigues

IPC分类号： H05K3/20 ,  H05K1/02 ,  H05K3/46

CPC分类号： H05K1/024 ,  H05K3/4602 ,  H05K3/4697 ,  Y10T29/49124 ,  Y10T29/49155

摘要： In a particular embodiment, a method of manufacturing a printed circuit board (‘PCB’) with reduced dielectric loss includes fabricating conductive traces disposed upon layers of dielectric material; and fabricating the layers of dielectric material, including core layers and prepreg layers, with one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB. In the particular embodiment, the conductive traces are disposed upon layers of the dielectric material orthogonally with respect to one another and the pockets of air are aligned at an angle of 45 degrees with respect to the conductive traces.

摘要翻译： 在特定实施例中，制造具有降低的介电损耗的印刷电路板（“PCB”）的方法包括制造设置在电介质材料层上的导电迹线; 以及制造包括芯层和预浸料层的介电材料层，其中一个或多个介电材料层包括空气袋，其减小PCB的总体相对介电常数。 在特定实施例中，导电迹线相对于彼此正交地布置在电介质材料的层上，并且空气袋相对于导电迹线以45度的角度对准。