公开(公告)号：US09277601B2

公开(公告)日：2016-03-01

申请号：US12393614

申请日：2009-02-26

Applicant: Justin P. Bandholz ,  Joseph E. Maxwell ,  Pravin Patel ,  Phillip L. Weinstein

Inventor： Justin P. Bandholz ,  Joseph E. Maxwell ,  Pravin Patel ,  Phillip L. Weinstein

IPC: H05B1/02 ,  H05B6/64

CPC classification number: H05B6/6441

Abstract: Method and computer program product for using an RFID antenna of a cooking appliance to read a plurality of cooking instruction sets from a single RFID tag associated with a food product that is positioned to be cooked by the cooking appliance. The cooking appliance selects one of the plurality of cooking instruction sets that the cooking appliance is capable of performing. Furthermore, the cooking appliance may then automatically cook the food product by controlling the cooking appliance according to the selected cooking instruction set. The selection of a cooking instruction set may consider the temperature of the food product or a determination whether the food product is frozen. Alternatively, cooking appliance settings may be interpolated between two cooking instruction sets or calculated on the basis of physical property information about the food product.

Abstract translation: 用于使用烹饪器具的RFID天线的方法和计算机程序产品从与烹饪器具定位烹饪的食品相关联的单个RFID标签读取多个烹饪指令集。 烹饪器具选择烹饪器具能够执行的多个烹饪指令集中的一个。 此外，烹饪器具然后可以根据所选择的烹饪指令集来控制烹饪器具来自动烹饪食品。 烹饪指导集的选择可以考虑食品的温度或者确定食品是否被冷冻。 或者，烹饪器具设置可以在两个烹饪指令集之间插值，或者基于关于食品的物理属性信息来计算。

公开(公告)号：US20120194992A1

公开(公告)日：2012-08-02

申请号：US13439221

申请日：2012-04-04

Applicant: Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

Inventor： Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

IPC: G06F1/16 ,  H05K3/30

CPC classification number: G06F1/185 ,  Y10T29/49147

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract translation: 一种DIMM转接卡，其包括具有第一边缘，第二边缘和一个或多个面部的PCB。 PCB的第一个边缘被配置为插入主板DIMM插槽。 第一个边缘包括电耦合到存储器总线的电迹线。 DIMM转接卡包括安装在PCB的一个面上的倾斜的DIMM插槽，其中倾斜的DIMM插槽被配置为以不垂直于PCB的角度接受DIMM并将DIMM电连接到存储器总线。 DIMM转接卡包括安装在PCB第二边缘上的跨骑式DIMM插槽。 跨骑式DIMM插槽被配置为接受DIMM并通过PCB第一边缘上的电迹线将DIMM电连接到存储器总线。

公开(公告)号：US08198878B2

公开(公告)日：2012-06-12

申请号：US12270989

申请日：2008-11-14

Applicant: Justin P. Bandholz ,  Pravin Patel ,  Philip L. Weinstein

Inventor： Justin P. Bandholz ,  Pravin Patel ,  Philip L. Weinstein

IPC: G05F1/00

CPC classification number: H02M3/1584

Abstract: Methods and apparatus for workload balancing among power switching components in a multiphase switching power supply, the power supply including one set of power switching components for each switching phase, where workload balancing includes: dropping one or more switching phases when output current demand on the power supply drops below a predetermined threshold, leaving at least one active switching phase; and rotating the at least one active switching phase among all sets of power switching components.

Abstract translation: 用于多相开关电源中的功率开关部件之间的工作负载平衡的方法和装置，所述电源包括用于每个开关阶段的一组功率开关组件，其中工作负载平衡包括：在输出电流对功率的需求时丢弃一个或多个开关阶段 供给下降到预定阈值以下，留下至少一个有效切换阶段; 以及在所有功率开关组件组之间旋转所述至少一个有源开关相位。

公开(公告)号：US08185682B2

公开(公告)日：2012-05-22

申请号：US11756656

申请日：2007-06-01

Applicant: Justin P. Bandholz ,  Robert J. Christopher ,  Joseph M. Jacobs ,  Pravin Patel

Inventor： Justin P. Bandholz ,  Robert J. Christopher ,  Joseph M. Jacobs ,  Pravin Patel

IPC: G06F13/14

CPC classification number: G06F13/4072

Abstract: A system for allowing a designer to implement Universal Serial Bus (USB) 2.0 in topologies not anticipated by a USB 2.0 specification and with reduced channel losses, the system comprising: a bus channel having a plurality of electrical elements; and a boost circuit connected at a predetermined location on the bus channel; a plurality of USB signals transmitted through the system; wherein edges of the plurality of USB signals are boosted without impacting the bi-directional nature of the bus channel.

Abstract translation: 一种用于允许设计者在USB 2.0规范未预期的拓扑中实现通用串行总线（USB）2.0和减少的信道损失的系统，该系统包括：具有多个电气元件的总线通道; 以及连接在所述总线通道上的预定位置处的升压电路; 通过系统传输的多个USB信号; 其中所述多个USB信号的边缘被提升而不影响所述总线信道的双向性质。

公开(公告)号：US07992030B2

公开(公告)日：2011-08-02

申请号：US11746102

申请日：2007-05-09

Applicant: Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

Inventor： Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

IPC: G06F1/00

CPC classification number: H03K5/1534 ,  H03K19/01721

Abstract: Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.

Abstract translation: 本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。 在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。 下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。 电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。 最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

公开(公告)号：US20110148543A1

公开(公告)日：2011-06-23

申请号：US12644704

申请日：2009-12-22

Applicant: Justin P. Bandholz ,  Pravin Patel ,  Peter R. Seidel

Inventor： Justin P. Bandholz ,  Pravin Patel ,  Peter R. Seidel

IPC: H03H7/38 ,  H01L21/66 ,  H01L23/52

CPC classification number: H01L24/48 ,  H01L22/14 ,  H01L22/20 ,  H01L23/645 ,  H01L24/45 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48092 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/20751 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An integrated circuit (IC) that includes a semiconductor die in an IC package. The semiconductor die includes an electrical endpoint. The IC also includes a pad affixed to the semiconductor die. The pad is characterized by a capacitance and is coupled to the electrical endpoint. The IC also includes a bond wire coupling the pad to an IC package pin. The bond wire is an inductor characterized by an inductance. The inductance is configured to decrease signal degradation caused by the capacitance of the pad on electrical signals transmitted between the pin and the electrical endpoint of the semiconductor die.

Abstract translation: 一种集成电路（IC），其包括IC封装中的半导体管芯。 半导体管芯包括电端点。 IC还包括固定到半导体管芯的焊盘。 焊盘的特征在于电容并且耦合到电端点。 IC还包括将焊盘耦合到IC封装引脚的接合线。 接合线是以电感为特征的电感器。 电感被配置为降低由在半导体管芯的引脚和电端点之间传输的电信号上的焊盘的电容引起的信号劣化。

公开(公告)号：US20110138095A1

公开(公告)日：2011-06-09

申请号：US12633441

申请日：2009-12-08

Applicant: Keith M. Campbell ,  Patrick L. Caporale ,  Caroline M. Metry ,  Pravin Patel

Inventor： Keith M. Campbell ,  Patrick L. Caporale ,  Caroline M. Metry ,  Pravin Patel

IPC: G06F13/00

CPC classification number: G06F13/409

Abstract: Settings are provided by a chassis management controller to an expansion card in a multi-slot server chassis. The chassis management controller in a multi-slot server chassis provides an operating parameter to a server management controller in a server, and the server management controller writes the operating parameter to a port expander of an expansion card installed on the server. The operating parameter is written to the port expander prior to expansion card power up, and the expansion card uses the operating parameter after power up to derive one or more SERDES value. The SERDES value is used to program an ASIC chip comprising a SERDES converter on the expansion card. In one example, the operating parameter is determined by the capabilities of a chassis midplane at the slot where the compute node is installed.

Abstract translation: 设备由机箱管理控制器提供给多插槽服务器机箱中的扩展卡。 多槽服务器机箱中的机箱管理控制器为服务器中的服务器管理控制器提供操作参数，服务器管理控制器将操作参数写入服务器上安装的扩展卡的端口扩展器。 在扩展卡上电之前，将操作参数写入端口扩展器，上电后扩展卡使用操作参数来导出一个或多个SERDES值。 SERDES值用于在扩展卡上对包含SERDES转换器的ASIC芯片进行编程。 在一个示例中，操作参数由在安装计算节点的时隙处的机箱中面板的能力确定。

公开(公告)号：US20100213187A1

公开(公告)日：2010-08-26

申请号：US12393614

申请日：2009-02-26

Applicant: Justin P. Bandholz ,  Joseph E. Maxwell ,  Pravin Patel ,  Phillip L. Weinstein

Inventor： Justin P. Bandholz ,  Joseph E. Maxwell ,  Pravin Patel ,  Phillip L. Weinstein

IPC: H05B1/02 ,  A47J27/00

CPC classification number: H05B6/6441

Abstract: Method and computer program product for using an RFID antenna of a cooking appliance to read a plurality of cooking instruction sets from a single RFID tag associated with a food product that is positioned to be cooked by the cooking appliance. The cooking appliance selects one of the plurality of cooking instruction sets that the cooking appliance is capable of performing. Furthermore, the cooking appliance may then automatically cook the food product by controlling the cooking appliance according to the selected cooking instruction set. The selection of a cooking instruction set may consider the temperature of the food product or a determination whether the food product is frozen. Alternatively, cooking appliance settings may be interpolated between two cooking instruction sets or calculated on the basis of physical property information about the food product.

Abstract translation: 用于使用烹饪器具的RFID天线的方法和计算机程序产品从与烹饪器具定位烹饪的食品相关联的单个RFID标签读取多个烹饪指令集。 烹饪器具选择烹饪器具能够执行的多个烹饪指令集中的一个。 此外，烹饪器具然后可以根据所选择的烹饪指令集来控制烹饪器具来自动烹饪食品。 烹饪指导集的选择可以考虑食品的温度或者确定食品是否被冷冻。 或者，烹饪器具设置可以在两个烹饪指令集之间插值，或者基于关于食品的物理属性信息来计算。

公开(公告)号：US20100124035A1

公开(公告)日：2010-05-20

申请号：US12274407

申请日：2008-11-20

Applicant: Justin P. Bandholz ,  Jonathan R. Hinkle ,  Pravin Patel

Inventor： Justin P. Bandholz ,  Jonathan R. Hinkle ,  Pravin Patel

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H05K1/0239 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09809

Abstract: A printed circuit board (‘PCB’) with a capacitor integrated within a via of the PCB, the PCB including layers of laminate; a via that includes a via hole traversing layers of the PCB, the via hole characterized by a generally tubular inner surface; a capacitor integrated within the via, the capacitor including two capacitor plates, an inner plate and an outer plate, the two plates composed of electrically conductive material disposed upon the inner surface of the via hole, both plates traversing layers of the laminate, the inner plate traversing more layers of the laminate than are traversed by the outer plate; and a layer of dielectric material disposed between the two plates.

Abstract translation: 印刷电路板（“PCB”），其电容器集成在PCB的通孔内，PCB包括层压板; 通孔，其包括穿过所述PCB的层的通孔，所述通孔的特征在于大致管状的内表面; 集成在通孔内的电容器，电容器包括两个电容器板，内板和外板，两个板由设置在通孔内表面上的导电材料组成，两个板横跨层压板，内部 板穿过层压板比由外板穿过的多层; 以及设置在两个板之间的介电材料层。

公开(公告)号：US20100123440A1

公开(公告)日：2010-05-20

申请号：US12270989

申请日：2008-11-14

Applicant: Justin P. Bandholz ,  Pravin Patel ,  Philip L. Weinstein

Inventor： Justin P. Bandholz ,  Pravin Patel ,  Philip L. Weinstein

IPC: G05F1/40

CPC classification number: H02M3/1584

Abstract: Methods and apparatus for workload balancing among power switching components in a multiphase switching power supply, the power supply including one set of power switching components for each switching phase, where workload balancing includes: dropping one or more switching phases when output current demand on the power supply drops below a predetermined threshold, leaving at least one active switching phase; and rotating the at least one active switching phase among all sets of power switching components.

Abstract translation: 用于多相开关电源中的功率开关部件之间的工作负载平衡的方法和装置，所述电源包括用于每个开关阶段的一组功率开关组件，其中工作负载平衡包括：在输出电流对功率的需求时丢弃一个或多个开关阶段 供给下降到预定阈值以下，留下至少一个有效切换阶段; 以及在所有功率开关组件组之间旋转所述至少一个有源开关相位。