公开(公告)号：US20240339991A1

公开(公告)日：2024-10-10

申请号：US18395790

申请日：2023-12-26

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Hao-Wei LIU ,  Yueh-Hua YU ,  Hong-Ren LIN

IPC: H03K3/03 ,  H03K3/014

CPC classification number: H03K3/0315 ,  H03K3/014

Abstract: A relaxation oscillator includes a start-up circuit. During the start-up period of the relaxation oscillator, two output signals from the relaxation oscillator are controlled to be complementary signals by the start-up circuit according to a control signal. Consequently, the relaxation oscillator can be started up successfully. The relaxation oscillator can generate periodic square wave signals. Moreover, during the start-up period of the relaxation oscillator, the generation of the deadlock situation can be avoided.

公开(公告)号：US20240296271A1

公开(公告)日：2024-09-05

申请号：US18244326

申请日：2023-09-11

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chin-Cheng CHEN ,  Jui-Hung HUNG ,  Jen-Hsing LIN

IPC: G06F30/392 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394

Abstract: A layout method, a non-transitory computer-readable medium, and an associated integrated circuit are provided. The non-transitory computer-readable medium records a software program for performing the layout method of the integrated circuit having Q circuit blocks. The layout method includes the following steps. K gate-controlled elements and (K−1) buffers are placed on the edge of a qth circuit block. The K gate-controlled elements are connected between a supply voltage terminal and the qth circuit block. (K−1) gate-controlled elements, including an SEL[1]-th gate-controlled element, are selected as (K−1) source nodes. Another (K−1) gate-controlled elements, other than the SEL[1]-th gate-controlled element, are selected as (K−1) destination nodes. The (K−1) buffers are routed as (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes.

公开(公告)号：US11831349B2

公开(公告)日：2023-11-28

申请号：US17575664

申请日：2022-01-14

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar Jain

IPC: H04B1/10 ,  H03K19/20 ,  H03K5/24

CPC classification number: H04B1/1018 ,  H03K5/24 ,  H03K19/20

Abstract: A serial signal detector and a differential signal detection method are provided. The serial signal detector includes a voltage comparison module and a hybrid logic filter. The voltage comparison module receives a differential signal, including a first shifted signal and a second shifted signal. The voltage comparison module includes a first comparator and a second comparator. Based on the first shifted signal, the second shifted signal, and a voltage threshold, the first and the second comparators respectively generate a first and a second comparison signals. The hybrid logic filter includes a controllable logic gate and a capacitor. The controllable logic gate performs a logic operation related to the first and the second comparison signals and generates a filtered and converted pulse accordingly. The controllable logic gate and the capacitor jointly perform a preliminary filtering operation to the filtered and converted pulse while the logic operation is being performed.

公开(公告)号：US20230351055A1

公开(公告)日：2023-11-02

申请号：US17899653

申请日：2022-08-31

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chun-Yuan LAI

IPC: G06F21/72 ,  H04L9/14 ,  H04L9/08 ,  H04L9/06 ,  G06F21/57

CPC classification number: G06F21/72 ,  H04L9/14 ,  H04L9/0894 ,  H04L9/0618 ,  G06F21/575 ,  G06F2221/034

Abstract: An SoC architecture includes a non-volatile memory and an SoC chip. The SoC chip is connected with the non-volatile memory. The SoC chip includes a central processing unit, a volatile memory, a system bus, an on-the-fly decryption circuit, a memory interface, a timer and a key bank. The on-the-fly decryption circuit is connected with the key bank. The on-the-fly decryption circuit performs an encryption operation or a decryption operation according to plural keys in the key bank. After the SoC architecture is powered on, if the timer is not disabled and the timer has counted time for a specified time period, the central processing unit is subjected to a warm reset, and a storage format in the non-volatile memory is changed from an initial format to an operation format by the central processing unit.

公开(公告)号：US11606091B2

公开(公告)日：2023-03-14

申请号：US17399312

申请日：2021-08-11

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chih-Hung Wu ,  Yu-Chieh Ma

IPC: H03K19/003

Abstract: An input/output module electrically coupled between a control circuit and an input/output pin is provided. The input/output module includes a pre-driver and a post-driver. The pre-driver is electrically coupled to the control circuit, and the post-driver is electrically coupled between the pre-driver and the input/output pin. The pre-driver generates a pull-up selection signal and a pull-down selection signal according to an input signal and an enable signal generated by the control circuit. The post-driver sets a voltage level of the input/output pin according to the pull-up and pull-down selection signals. When the enable signal is at a first logic level, the input/output pin has a high impedance. When the enable signal is at a second logic level, the voltage level of the input/output pin changes with a logic level of the input signal, wherein the first logic level and the second logic level are inverted.

公开(公告)号：US20230029065A1

公开(公告)日：2023-01-26

申请号：US17542531

申请日：2021-12-06

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Bu-Qing Ping

IPC: G06F13/42 ,  H04L69/324

Abstract: The invention provides a transaction layer circuit of a PCIe. The transaction layer circuit includes transaction layer processing channels, a channel selection circuit, and a merge circuit. The transaction layer processing channels are coupled to a data bus transmitting at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit receives packet start/end location information in a current clock cycle from the data link layer circuit, and distributes at least one packet data in the current clock cycle to at least one transaction layer processing channel according to the packet start/end location information. The merge circuit is coupled to the transaction layer processing channels and selectively merges transaction layer processing results output by the transaction layer processing channels based on the distribution of the packet data in the current clock cycle to the transaction layer processing channels via the channel selection circuit.

公开(公告)号：US11360709B1

公开(公告)日：2022-06-14

申请号：US16953549

申请日：2020-11-20

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Hong-Yi Wu ,  Sivaramakrishnan Subramanian ,  Sridhar Cheruku ,  Ko-Ching Chao

IPC: G06F3/06 ,  G06F13/16 ,  G11C11/4076

Abstract: A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.

公开(公告)号：US20210305990A1

公开(公告)日：2021-09-30

申请号：US17151673

申请日：2021-01-19

Applicant: FARADAY TECHNOLOGY CORPORATION ,  Faraday Technology Corp.

Inventor： Feng Xu ,  Chih-Yuan Hung ,  MENG ZHAO

IPC: H03M1/06

Abstract: A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.

公开(公告)号：US20210048861A1

公开(公告)日：2021-02-18

申请号：US16709021

申请日：2019-12-10

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Kun-Hua Huang ,  Chang-Chin CHUNG ,  Kun-Chih CHEN

IPC: G06F1/24 ,  H03K19/20 ,  G06F1/04 ,  G06F13/42

Abstract: A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.

公开(公告)号：US10797683B1

公开(公告)日：2020-10-06

申请号：US16811371

申请日：2020-03-06

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar Jain ,  Chi-Yeu Chao ,  Prateek Kumar Goyal ,  Han-Kyul Lim

IPC: H03K3/017 ,  H03K5/156 ,  G06F1/04

Abstract: A calibration circuit, including a duty cycle correction circuit and a phase correction circuit and associated calibrating method, are provided. Firstly, a first duty cycle adjusted clock and a second duty cycle adjusted clock are generated by the duty cycle correction circuit based on a first input clock and a second input clock, respectively. Then, a first delay adjusted clock and a second delay adjusted clock are generated by the phase correction circuit based on a phase of the first duty cycle adjusted clock, and a detection signal is generated. The detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock. Later, the duty cycle correction circuit and the phase correction circuit are controlled in response to the detection signal.