Apparatus for controlling access, by processing devices, to memories in an embedded system
    21.
    发明申请
    Apparatus for controlling access, by processing devices, to memories in an embedded system 审中-公开
    用于通过处理设备来控制对嵌入式系统中的存储器的访问的装置

    公开(公告)号:US20060069880A1

    公开(公告)日:2006-03-30

    申请号:US11235463

    申请日:2005-09-26

    CPC classification number: G06F13/1663

    Abstract: The present invention provides an apparatus for controlling access, by processing devices to memories in an embedded system, with the apparatus being arranged between the processing devices and the memories, and with the apparatus independently moving data between the memories and between the memories and internal memories in the processing devices.

    Abstract translation: 本发明提供了一种用于通过将设备处理到嵌入式系统中的存储器来控制访问的装置,其中装置被布置在处理装置和存储器之间,并且该装置在存储器之间以及存储器和内部存储器之间独立地移动数据 在处理装置中。

    Method and apparatus for mapping applications to radios in a wireless communication device
    22.
    发明授权
    Method and apparatus for mapping applications to radios in a wireless communication device 有权
    用于将应用映射到无线通信设备中的无线电的方法和装置

    公开(公告)号:US09185719B2

    公开(公告)日:2015-11-10

    申请号:US12857686

    申请日:2010-08-17

    CPC classification number: H04W72/1215 H04W48/18 H04W88/06

    Abstract: Techniques for mapping applications to radios in a wireless communication device are described. In one design, a controller residing below an operating system may receive inputs from applications residing above the operating system. The controller may determine radios selected based on the application inputs and further to mitigate interference between these radios. The controller may determine mapping of the applications to the radios based on the application inputs and may provide, to the applications, information indicative of the radios to which the applications are mapped. The applications may obtain connectivity via their selected radios. The controller may interface with entities in both upper layers and lower layers to facilitate radio selection and application-to-radio mapping. The controller may control the operation of a connection manager and/or a coexistence manager, manage databases for these managers, provide CPU and memory resources for these managers, manage a data bus used for communication, etc.

    Abstract translation: 描述了将应用映射到无线通信设备中的无线电的技术。 在一种设计中,位于操作系统下方的控制器可以接收来自驻留在操作系统上方的应用的输入。 控制器可以基于应用输入来确定选择的无线电,并进一步减轻这些无线电之间的干扰。 控制器可以基于应用输入来确定应用到无线电的映射,并且可以向应用提供指示应用映射到的无线电的信息。 应用程序可以通过其选定的无线电获取连接。 控制器可以与上层和下层的实体进行接口,以便于无线电选择和应用到无线电映射。 控制器可以控制连接管理器和/或共存管理器的操作,管理这些管理器的数据库,为这些管理器提供CPU和存储器资源,管理用于通信的数据总线等。

    Diesel cycle internal combustion engine
    24.
    发明授权
    Diesel cycle internal combustion engine 有权
    柴油循环内燃机

    公开(公告)号:US07954477B2

    公开(公告)日:2011-06-07

    申请号:US12306263

    申请日:2007-06-27

    Abstract: A diesel cycle internal combustion engine can be operated with a variety of fuels having different boiling points and different viscosity-temperature characteristic curves, with a fuel circuit that includes a fuel tank, a fuel pump, a fuel line, at least one fuel filter, a high-pressure pump, an injection system device and a return line to return fuel to the fuel tank, where a control valve is provided in the return line for dividing or diverting the fuel flow to the fuel tank and/or to the fuel filter, and where the fuel division or diversion is undertaken as a function of the viscosity of the fuel in use such that the fuel filter will thence be heated to a temperature based on heat transfer from the fuel in use, and further where a pressure relief valve is provided between the fuel filter and the high-pressure pump.

    Abstract translation: 柴油循环内燃机可以用具有不同沸点和不同粘度 - 温度特性曲线的各种燃料操作,燃料回路包括燃料箱,燃料泵,燃料管线,至少一个燃料过滤器, 高压泵,注射系统装置和返回管线以将燃料返回到燃料箱,其中控制阀设置在返回管线中,用于将燃料流分配或转向燃料箱和/或燃料过滤器 ,并且在燃料分配或转向作为使用的燃料的粘度的函数的情况下,使得燃料过滤器将被加热到基于使用中的燃料的热传递的温度,并且还有其中压力释放阀 设置在燃料过滤器和高压泵之间。

    SLEEP MODE DESIGN FOR COEXISTENCE MANAGER
    25.
    发明申请
    SLEEP MODE DESIGN FOR COEXISTENCE MANAGER 审中-公开
    休闲模式设计为​​共同经理

    公开(公告)号:US20110007680A1

    公开(公告)日:2011-01-13

    申请号:US12616074

    申请日:2009-11-10

    Abstract: Systems and methodologies are described herein that facilitate implementation and use of a sleep mode for a multi-radio coexistence manager. As described herein, respective radios coordinated by a coexistence manager (CxM) can be grouped into radio or sleep clusters, for which the CxM can enter a low-power mode (e.g., a sleep mode) based on respective operating states of radios in the clusters. As further described herein, a CxM can provide an acquisition sequence and/or other suitable means to enable respective radios to synchronize with the CxM. In addition, techniques are provided herein by which a CxM can indicate its present operating mode (e.g., active, wakeable sleep, non-wakeable sleep, or disabled) to respective radios, and by which a radio can wake the CxM from a sleep operating mode under predetermined circumstances.

    Abstract translation: 本文描述了便于多无线电共存管理器的睡眠模式的实现和使用的系统和方法。 如本文所描述的,由共存管理器(CxM)协调的相应无线电可以被分组成无线电或睡眠群集,基于其中的无线电的相应操作状态,CxM可以进入低功率模式(例如,睡眠模式) 集群。 如本文进一步描述的,CxM可以提供采集序列和/或其他合适的装置,以使各个无线电与CxM同步。 此外,本文提供了一种技术,通过该技术,CxM可以向相应的无线电装置指示其当前的操作模式(例如,活动的,可唤醒的睡眠,不可唤醒的睡眠或禁用的),并且无线电可以通过该技术将CxM从睡眠操作中唤醒 模式在预定的情况下。

    Multiprocessor system having a shared tightly coupled memory and method for communication between a plurality of processors
    26.
    发明授权
    Multiprocessor system having a shared tightly coupled memory and method for communication between a plurality of processors 有权
    具有共享紧密耦合存储器的多处理器系统和用于在多个处理器之间进行通信的方法

    公开(公告)号:US07797496B2

    公开(公告)日:2010-09-14

    申请号:US10941119

    申请日:2004-09-15

    CPC classification number: G06F15/16

    Abstract: A multiprocessor system comprises a first processor (P1) and a second processor (P2) each having an input/output set up for the connection of a tightly coupled semiconductor memory. Furthermore, the multiprocessor system comprises a shared tightly coupled integrated semiconductor memory (101), which can be accessed by both processors (P1, P2) via their input/output.

    Abstract translation: 多处理器系统包括第一处理器(P1)和第二处理器(P2),每个处理器具有设置用于连接紧耦合半导体存储器的输入/输出。 此外,多处理器系统包括可由两个处理器(P1,P2)经由其输入/输出访问的共享紧耦合集成半导体存储器(101)。

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