公开(公告)号：US4814756A

公开(公告)日：1989-03-21

申请号：US9578

申请日：1987-01-28

申请人： Gerard Chauvel

发明人： Gerard Chauvel

IPC分类号： G06F5/10 ,  G06F5/12 ,  G06F5/14 ,  G09G5/34 ,  G09G5/40 ,  H04N7/025 ,  H04N7/035 ,  G09G1/16

CPC分类号： G06F5/14 ,  G06F5/12 ,  G09G5/343 ,  G09G5/40 ,  H04N7/0255 ,  H04N7/035 ,  G06F2205/123

摘要： A system for displaying alphanumeric and graphic information on a raster scanned display device, for example, in a teletext system, includes a memory which is updated to change the display. Dynamic changes in the displayed image are provided by assigning a base address to each of one or more zones in the memory and altering the base addresses as required under local or remote control. Alphanumeric and graphic data may be combined on a single displayed page by means of identification data associated with each row or line of data to be displayed. The required capacity of the memory associated with the display device is substantially reduced by assigning a control code to data which is to be repetitively displayed, for example, spaces at the end of a line or fields of uniform color. Selected elements are thus displayed a predetermined number of times without the need for a corresponding number of memory locations. Incoming data may be sotred in a buffer memory at a greater rate than can be processed by the present system by means of a control circuit which inhibits the inputting of data for a period of time when there is a risk of overwriting or erasure of previously stored data.

摘要翻译： 用于在例如图文电视系统中的光栅扫描显示设备上显示字母数字和图形信息的系统包括更新以改变显示的存储器。 通过为存储器中的一个或多个区域中的每一个分配基地址并且在本地或远程控制下根据需要改变基地址来提供所显示图像的动态变化。 字母数字和图形数据可以通过与要显示的每行或数据行相关联的标识数据组合在单个显示页面上。 通过将控制代码分配给要重复显示的数据（例如在一行或多个均匀颜色的场的空格）来显着减少与显示设备相关联的存储器的所需容量。 所选择的元件因此显示预定次数，而不需要相应数量的存储器位置。 输入数据可以以比当前系统可以通过控制电路更大的速率被存储在缓冲存储器中，该控制电路在存在重写或擦除先前存储的风险的一段时间内禁止输入数据 数据。

公开(公告)号：US4684938A

公开(公告)日：1987-08-04

申请号：US583072

申请日：1984-02-23

申请人： Gerard Chauvel

发明人： Gerard Chauvel

IPC分类号： G09G5/36 ,  G09G5/39 ,  G09G1/16

CPC分类号： G09G5/363

摘要： A system for visualization on a video screen (6) in a graphical mode in which the visual information to be displayed is defined on the screen by a point by point sweeping, from page memory containing, at a given time, all of the video information to be displayed, and a video display processor (4), connected to a random access memory containing said page memory and to a display control unit (37) adapted to convert the information relative to the image composed from the contents of the memory (5) to screen (6) control signals, characterized in that central processing unit (1) is connected to the video display processor (4) by means of a single bus (12) over which are transmitted, on a time shared basis, the address fields and the data fields (15) and in that it includes in addition a control and interpretation circuit (27) capable, in response to an assignment signal generated by said central processing unit, to interpret the address field as an address field per se or as a control field for the video display processor.

摘要翻译： 一种用于以图形模式在视频屏幕（6）上可视化的系统，其中通过逐点扫描在屏幕上定义要显示的视觉信息，从包含在给定时间的所有视频信息的页面存储器 以及连接到包含所述页面存储器的随机存取存储器的视频显示处理器（4）和适于将信息相对于由存储器（5）的内容构成的图像转换的显示控制单元（37） ）屏幕（6）控制信号，其特征在于，中央处理单元（1）通过单个总线（12）连接到视频显示处理器（4），在该总线（​​12）上以时间共享方式发送地址 字段和数据字段（15），并且其还包括控制和解释电路（27），其能够响应于由所述中央处理单元生成的分配信号将地址字段解释为地址字段本身或 作为控制领域 用于视频显示处理器。

公开(公告)号：US4240138A

公开(公告)日：1980-12-16

申请号：US948284

申请日：1978-10-03

申请人： Gerard Chauvel

发明人： Gerard Chauvel

IPC分类号： G06F13/16 ,  G06F13/28 ,  G06F3/00

CPC分类号： G06F13/1673 ,  G06F13/287

摘要： System for direct access to a memory associated with a microprocessor data processing device comprising a direct access interface for introducing or extracting data in the memory during interruptions of the connection between the processing device and the memory, and a buffer interface operable during a portion of the access time of the processing device to the memory, to supply data addresses contained in the memory originating from the processing device and to enable circulation of corresponding data between the processing device and the memory, and during the remainder of the access time of the processing device, to the end of the access time, to store data transferred from the memory and to prevent transmission of data to the memory. A logic circuit controls inhibition of the buffer interface or of the direct access interface and, during the periods of inhibition of the buffer interface, permits the circulation of data and of addresses between the direct access interface and the memory.

摘要翻译： 用于直接访问与微处理器数据处理设备相关联的存储器的系统，包括用于在处理设备和存储器之间的连接中断期间在存储器中引入或提取数据的直接访问接口，以及可在一部分 提供处理设备到存储器的访问时间，以提供包含在来自处理设备的存储器中的数据地址，并且能够在处理设备和存储器之间以及在处理设备的访问时间的剩余时间期间循环相应的数据 在访问时间结束时，存储从存储器传送的数据并防止数据传送到存储器。 逻辑电路控制对缓冲器接口或直接访问接口的禁止，并且在缓冲器接口的禁止期间允许在直接访问接口和存储器之间的数据和地址的循环。

公开(公告)号：US08516496B2

公开(公告)日：2013-08-20

申请号：US11186315

申请日：2005-07-21

申请人： Gilbert Cabillic ,  Gerard Chauvel

发明人： Gilbert Cabillic ,  Gerard Chauvel

IPC分类号： G06F9/46 ,  G06F15/00

CPC分类号： G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

摘要： An electronic device comprising decode logic that decodes instructions and a stack coupled to the decode logic. A group of instructions causes the decode logic to push onto the stack, after halting processing of a first thread at a switch point and prior to processing a second thread, a minimum amount of information needed to resume execution of the first thread at the switch point and not information not needed to resume execution of the first thread at the switch point.

摘要翻译： 一种电子设备，包括解码逻辑，其解码指令和耦合到解码逻辑的堆栈。 一组指令使解码逻辑推到堆栈上，在停止处理切换点处的第一线程并且在处理第二线程之前，在切换点恢复执行第一线程所需的最少量的信息 而不是在切换点恢复执行第一个线程所需的信息。

公开(公告)号：US08190861B2

公开(公告)日：2012-05-29

申请号：US11677367

申请日：2007-02-21

申请人： Gerard Chauvel ,  Gilbert Cabillic ,  Jean-Philippe Lesot ,  Dominique D'Inverno ,  Eric Badi ,  Serge Lasserre

发明人： Gerard Chauvel ,  Gilbert Cabillic ,  Jean-Philippe Lesot ,  Dominique D'Inverno ,  Eric Badi ,  Serge Lasserre

IPC分类号： G06F9/00

CPC分类号： G06F9/4812

摘要： A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex security model in JSM code by implementing a micro-sequence security trigger. The method includes micro-sequence based security policy that determines whether an instruction accesses a privileged resource associated with a processor and when not already in privilege mode and not executing a micro-sequence, the micro-sequence based security policy is applied to the instruction to control access to the privileged resource according to the security policy.

摘要翻译： 一种用于在处理器中实现基于微序列的安全模型的方法和系统。 更具体地，使用微序列和JSM硬件资源来构建对应用不可见的安全模型，并且当存储器约束到位时，通过实现微序列安全触发来扩展JSM代码中的复杂安全模型。 该方法包括基于微序列的安全策略，其确定指令是否访问与处理器相关联的特权资源，以及当尚未处于特权模式且不执行微序列时，将基于微序列的安全策略应用于 根据安全策略控制对特权资源的访问。

公开(公告)号：US07757223B2

公开(公告)日：2010-07-13

申请号：US11188502

申请日：2005-07-25

申请人： Gilbert Cabillic ,  Jean-Philippe Lesot ,  Mikael Peltier ,  Gerard Chauvel

发明人： Gilbert Cabillic ,  Jean-Philippe Lesot ,  Mikael Peltier ,  Gerard Chauvel

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

摘要： The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.

摘要翻译： 上述问题在很大程度上是由现有硬件资源和软件构成用于字节码验证器的数据流分析器的方法和系统。 具体来说，可以采用微序列和JSM硬件资源来取得第一指令，将第一指令应用于处理器的解码逻辑，由解码逻辑触发第一系列指令的执行，该解码逻辑从数据中弹出第一值 结构，例如堆栈或局部变量映射，指示通过先前解码的指令来推送在堆栈上的参数类型的第一值或局部变量映射; 并验证第一个值是第一个指令预期的参数类型。

公开(公告)号：US07712098B2

公开(公告)日：2010-05-04

申请号：US10157773

申请日：2002-05-29

申请人： Gerard Chauvel ,  Serge Lasserre ,  Edward E. Ferguson

发明人： Gerard Chauvel ,  Serge Lasserre ,  Edward E. Ferguson

IPC分类号： G06F9/46 ,  G06F12/00

CPC分类号： G06F9/5016 ,  G06F12/1036 ,  G06F2212/681

摘要： A digital system and method of operation is provided in which several processors (440, 450) are connected to a shared memory resource (460). Translation lookaside buffers (TLB) (400, 402) are connected to receive a request address (404a-n) from each respective processor. Each TLB has a set of entries that correspond to pages of address space. Each entry provides a set of task memory attributes (TMA) (412a-n) for the associated page of address space. Task memory attributes are defined by a task control block associated with a currently executing task. For each memory transfer request, the TLB accesses an entry corresponding to the request address and provides a translated physical memory address and a task memory attribute value associated with that requested address space page. Functional circuitry (470) performs pre/post-processing on data that is being transferred between a processor and the memory in accordance with the task memory attribute value provided by the TLB with each memory transfer request. Thus, data accessed at the same address by different tasks on a same processor or on different processors can be pre-processed or post-processed in a manner defined by a task control block. Such pre/post-processing may include compression/decompression, encryption/decryption, or formatting, for example.

摘要翻译： 提供了数字系统和操作方法，其中几个处理器（440,450）连接到共享存储器资源（460）。 翻转后备缓冲器（TLB）（400,402）被连接以从每个相应的处理器接收请求地址（404a-n）。 每个TLB具有一组对应于地址空间的页面的条目。 每个条目为相关联的地址空间页面提供一组任务存储器属性（TMA）（412a-n）。 任务存储器属性由与当前执行的任务相关联的任务控制块定义。 对于每个存储器传送请求，TLB访问与请求地址相对应的条目，并提供翻译的物理存储器地址和与该请求的地址空间页相关联的任务存储器属性值。 功能电路（470）根据TLB与每个存储器传送请求提供的任务存储器属性值对处理器和存储器之间传输的数据执行预处理/后处理。 因此，可以以相同处理器或不同处理器上的不同任务在相同地址处访问的数据以任务控制块定义的方式进行预处理或后处理。 这种预处理/后处理可以包括例如压缩/解压缩，加密/解密或格式化。

公开(公告)号：US07624382B2

公开(公告)日：2009-11-24

申请号：US11189367

申请日：2005-07-26

申请人： Gerard Chauvel ,  Jean-Philippe Lesot ,  Gilbert Cabillic ,  Mikael Peltier

发明人： Gerard Chauvel ,  Jean-Philippe Lesot ,  Gilbert Cabillic ,  Mikael Peltier

IPC分类号： G06F9/44

CPC分类号： G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

摘要： A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction from a memory, the instruction being part of a program, and decode logic coupled to the fetch logic which decodes the instruction, wherein the instruction decoded by the decode logic triggers execution of a micro-sequence to enter the instruction in a control flow graph.

摘要翻译： 一种通过使用硬件执行微序列构建控制流程图的方法和系统。 一些说明性实施例是包括从存储器检索指令的获取逻辑的处理器，作为程序的一部分的指令以及耦合到解码指令的取指逻辑的解码逻辑，其中由解码逻辑解码的指令触发执行 微序列在控制流程图中输入指令。

公开(公告)号：US07574584B2

公开(公告)日：2009-08-11

申请号：US11186239

申请日：2005-07-21

申请人： Gerard Chauvel ,  Maija Kuusela

发明人： Gerard Chauvel ,  Maija Kuusela

IPC分类号： G06F9/00 ,  G06F7/42

CPC分类号： G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

摘要： In some embodiments, a processor includes fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to software and partly in the hardware state machine. For a floating point add instruction, mantissa addition is executed in the integer pipeline and the plurality of operations performed by the hardware state machine includes testing of exponents, testing for overflow and underflow conditions, packing, and rounding detection.

摘要翻译： 在一些实施例中，处理器包括取指令，整数流水线以及与整数流水线分开并与其整体流水线相互作用的硬件状态机。 该指令根据软件部分在整数流水线中执行，部分在硬件状态机中执行。 对于浮点加法指令，在整数流水线中执行尾数加法，并且由硬件状态机执行的多个操作包括指数的测试，溢出和下溢条件的测试，打包和舍入检测。

公开(公告)号：US07555611B2

公开(公告)日：2009-06-30

申请号：US10632076

申请日：2003-07-31

申请人： Serge Lasserre ,  Maija Kuusela ,  Gerard Chauvel

发明人： Serge Lasserre ,  Maija Kuusela ,  Gerard Chauvel

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/0253 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/502 ,  Y02D10/13

摘要： A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java local variables) may be stored in the data memory. The data memory preferably is adapted to store two groups of local variables. A first group comprises local variables associated with finished methods and a second group comprises local variables associated with unfinished methods. Further, local variables are saved to, or fetched from, external memory upon a context change based on a threshold value differentiating the first and second groups. The first value may comprise a threshold address or an allocation bit associated with each of a plurality of lines forming the data memory.

摘要翻译： 缓存子系统可以包括多路组关联高速缓存和数据存储器，其保存由存储在寄存器中的地址定义的连续的存储块。 局部变量（例如，Java局部变量）可以存储在数据存储器中。 数据存储器优选地适于存储两组局部变量。 第一组包括与完成的方法相关联的局部变量，第二组包括与未完成方法相关联的局部变量。 此外，基于区分第一和第二组的阈值，在上下文改变时，将局部变量保存到外部存储器或从外部存储器获取。 第一值可以包括与形成数据存储器的多条线中的每一条相关联的阈值地址或分配位。