Abstract:
Disclosed is a liquid crystal display capable of high quality image and bright display. Gate signal lines are curved at near switching elements of the liquid crystal display. A pixel area is defined by the gate signal lines and their intersecting data signal lines. Pixel electrodes and common electrodes are disposed along a longitudinal direction of a pixel. A pixel signal and a common signal line is connected to the pixel electrode and the common electrode respectively. A storage capacitor may be formed in the middle of a longitudinal direction of the pixel, or where generally a texture may arise during display. One half of the pixel may be symmetrical with the other half with respect to the storage capacitor. A common signal line may be parallel with the data signal line and be disposed nearer to the data signal line than a pixel signal line. The pixel may be disposed symmetrically with respect to the data signal line therebetween. The pixel shape may also be repeated in the direction of the gate signal line.
Abstract:
The disclosure describes a liquid crystal display panel including a plurality of sub-pixels, a plurality of thin film transistors, a plurality of data lines, and a plurality of gate lines. Each of the sub-pixels has first and second gray scale regions which are split up and down and have different areas, first and second gray scale regions of one sub-pixel having a staggered arrangement with respect to those of an adjacent sub-pixel. Thin film transistors are connected to first and second gray scale regions so that first gray scale regions are driven when one of gate lines is driven and the second gray scale regions are driven when another gate line is driven.
Abstract:
A liquid crystal display includes a first substrate, a gate line, a data line, first-third power lines located on the first substrate, first-third sub-pixels, where a switching element of each is connected to the gate line and the data line, a second substrate, a common electrode that is formed on the second substrate, a liquid crystal layer located between the first and second substrates, and a power voltage driver outputting a low voltage during a first period and a high voltage during a subsequent second period to the first power line, a constant voltage during both periods to the second power line, and the high voltage during the first period and the low voltage during the second period to the third power line. The first power line, the second power line and the third power line overlap the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively.
Abstract:
In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.
Abstract:
A liquid crystal display includes: a substrate; a pixel electrode disposed on the substrate and having a first subpixel electrode and a second subpixel electrode; and a common electrode facing the pixel electrode, wherein the first subpixel electrode has a pair of bent edges substantially parallel to each other, the second subpixel electrode has a pair of bent edges substantially parallel to each other, and the second subpixel electrode has a height greater than a height of the first subpixel electrode.
Abstract:
A liquid crystal display includes a substrate, a pixel electrode disposed on the substrate and including a first subpixel electrode and a second subpixel electrode, and a common electrode facing the pixel electrode. The first subpixel electrode comprises a first edge, a second edge disposed opposite the first edge, and two first oblique edges substantially parallel to each other, the first oblique edges making an oblique angle with the first edge and the second edge and meeting the first edge. The second subpixel electrode comprises a first edge, a second edge disposed opposite the first edge, and two first oblique edges substantially parallel to or substantially perpendicular to the first oblique edges of the first subpixel electrode, the first oblique edges of the second subpixel electrode meeting the first edge of the second subpixel electrode. The first edge of the first subpixel electrode is adjacent to the first edge of the second subpixel electrode, and a length of the first edge of the first subpixel electrode is different from a length of the first edge of the second subpixel electrode. The first oblique edges of the first subpixel electrode are offset from the first oblique edges of the second subpixel electrode.
Abstract:
A liquid crystal display is provided, which includes: a plurality of pixels; a gray voltage generator generating a plurality of gray voltages; an image signal modifier that receives first, second, and third image signals for a pixel in three successive frames, generates a preliminary signal for the second image signal based on the first image signal, and generates a modified signal for the second image signal based on the preliminary signal and the third image signal; and a data driver converting the modified signal into a data voltage selected from the gray voltages and applying the data voltage to the pixel, wherein a range of the gray voltages is substantially equal to a range of target voltages for obtaining target luminance of the pixel, and a highest available value for the modified signal is equal to a highest available value of the image signals.
Abstract:
A liquid crystal display panel includes a plurality of sub-pixels, a plurality of thin film transistors, a plurality of data lines, and a plurality of gate lines. Each of the sub-pixels have first and second gray scale regions which are split up and down and have different areas, the first and second gray scale regions of one sub-pixel having a staggered arrangement with respect to those of an adjacent sub-pixel. Thin film transistors are connected to the first and second gray scale regions so that the first gray scale regions are driven when one of gate lines is driven and the second gray scale regions are driven when another gate line is driven.
Abstract:
A display apparatus comprises a plurality of pixel areas, each defined by gate lines and data lines, wherein the data lines are arranged with the gate lines forming an angular relationship with the data lines, and a plurality of pixel electrodes formed in the pixel areas and configured to be essentially parallel with the arrangement of the gate lines.
Abstract:
A liquid crystal display that includes a substrate; a plurality of gate lines formed on the substrate; a plurality of common electrodes formed on the substrate and made of a transparent material; a plurality of data lines intersecting the gate lines; a plurality of thin film transistors connected to the data lines and the gate lines; and a plurality of pixel electrodes connected to the thin film transistors and overlapping the common electrodes. The pixel electrodes include a first sub-pixel electrode separated by a distance from a second sub-pixel electrode.