公开(公告)号：US07902847B2

公开(公告)日：2011-03-08

申请号：US12482560

申请日：2009-06-11

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G01R31/02

CPC分类号： G01R31/318335 ,  G01R31/31712 ,  G01R31/31724 ,  G01R31/318511

摘要： A semiconductor device includes: a command control circuit for decoding a command signal to output a test signal and a normal control signal; a normal circuit for performing a predetermined operation in response to the normal control signal; and a test circuit for testing electrical characteristics of unit elements provided in the normal circuit in response to the test signal.

摘要翻译： 半导体器件包括：命令控制电路，用于解码命令信号以输出测试信号和正常控制信号; 用于响应于正常控制信号执行预定操作的正常电路; 以及用于测试响应于测试信号在普通电路中提供的单元的电特性的测试电路。

公开(公告)号：US07719916B2

公开(公告)日：2010-05-18

申请号：US12003685

申请日：2007-12-31

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/401 ,  G11C11/40611 ,  G11C11/40615 ,  G11C29/02 ,  G11C29/50016

摘要： A semiconductor memory device includes a command decoder, a refresh address counter, an address delivery unit, and an address output selector. The command decoder decodes a command signal to generate a refresh signal. The refresh address counter generates a refresh address in response to the refresh signal. The address delivery unit delivers one of the refresh address and an address from outside of the semiconductor memory device to a memory core area. The address output selector outputs the refresh address to the outside of the semiconductor memory device.

摘要翻译： 半导体存储器件包括命令解码器，刷新地址计数器，地址传递单元和地址输出选择器。 命令解码器解码命令信号以产生刷新信号。 刷新地址计数器响应于刷新信号产生刷新地址。 地址传送单元将刷新地址和地址从半导体存储器件的外部传送到存储器核心区域。 地址输出选择器将刷新地址输出到半导体存储器件的外部。

公开(公告)号：US20100054050A1

公开(公告)日：2010-03-04

申请号：US12325364

申请日：2008-12-01

申请人： Jun-Hyun CHUN

发明人： Jun-Hyun CHUN

IPC分类号： G11C11/406 ,  G11C5/14 ,  G11C7/12

CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C2211/4067

摘要： An apparatus for applying power in a semiconductor memory device includes a first power pin for receiving a first power at a first voltage from an external device, a second power pin for receiving a second power at the first voltage, a memory array block connected to the first power pin, the memory array block writing input data, outputting read data, and refreshing regularly to sustain stored data, a peripheral logic block connected to the first power pin for receiving the first power and communicating with the memory array block to perform data write and read operations, a data output driver connected to the second power pin and driving a data output pin, and a switch for electrically connecting the first power pin and the second power pin by performing a switching operation during a refresh operation of the memory array block.

摘要翻译： 一种用于在半导体存储器件中施加电力的设备包括：第一电源管脚，用于从外部设备接收第一电压的第一电力;第二电源管脚，用于在第一电压下接收第二电力;存储器阵列块， 第一电源引脚，存储器阵列块写入输入数据，输出读取数据和定期刷新以维持存储的数据;连接到第一电源引脚的外围逻辑块，用于接收第一电力并与存储器阵列块通信以执行数据写入 读取操作，连接到第二电源引脚并驱动数据输出引脚的数据输出驱动器和用于通过在存储器阵列块的刷新操作期间执行切换操作来电连接第一电源引脚和第二电源引脚的开关 。

公开(公告)号：US20080239853A1

公开(公告)日：2008-10-02

申请号：US12003685

申请日：2007-12-31

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C11/401 ,  G11C11/40611 ,  G11C11/40615 ,  G11C29/02 ,  G11C29/50016

摘要： A semiconductor memory device includes a command decoder, a refresh address counter, an address delivery unit, and an address output selector. The command decoder decodes a command signal to generate a refresh signal. The refresh address counter generates a refresh address in response to the refresh signal. The address delivery unit delivers one of the refresh address and an address from outside of the semiconductor memory device to a memory core area. The address output selector outputs the refresh address to the outside of the semiconductor memory device.

摘要翻译： 半导体存储器件包括命令解码器，刷新地址计数器，地址传递单元和地址输出选择器。 命令解码器解码命令信号以产生刷新信号。 刷新地址计数器响应于刷新信号产生刷新地址。 地址传送单元将刷新地址和地址从半导体存储器件的外部传送到存储器核心区域。 地址输出选择器将刷新地址输出到半导体存储器件的外部。

公开(公告)号：US07236420B2

公开(公告)日：2007-06-26

申请号：US10511253

申请日：2003-04-10

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G11C8/00

CPC分类号： G11C5/025 ,  G11C8/12 ,  G11C2207/105

摘要： A semiconductor memory device having semiconductor memory chips, each semiconductor memory chip includes a plurality of memory banks capable of independently to be accessed, each memory bank having a plurality of memory blocks, wherein at least two memory blocks, which are neighbored each other in the same memory bank, have the different number of unit memory blocks, so that each bank has a non-rectangular shape.

摘要翻译： 一种具有半导体存储器芯片的半导体存储器件，每个半导体存储器芯片包括能够独立地被访问的多个存储器组，每个存储体具有多个存储器块，其中至少两个存储块彼此相邻 相同的存储体，具有不同数量的单位存储块，使得每个存储体具有非矩形形状。

公开(公告)号：US5764652A

公开(公告)日：1998-06-09

申请号：US723244

申请日：1996-09-30

申请人： Jun Hyun Chun

发明人： Jun Hyun Chun

IPC分类号： H01L21/82 ,  G11C29/00 ,  G11C29/04 ,  G11C29/18 ,  G06F11/00

CPC分类号： G11C29/842

摘要： A repair circuit of a semiconductor memory device is disclosed, including an address input unit for receiving and processing external addresses; a repair detecting unit for detecting whether there are addresses repaired on a programmed data basis; a normal decoding unit for selecting normal word lines; a redundant decoding unit for selecting redundant word lines; a repair address determining unit, enabled by a signal produced from the repair detecting unit, for comparing the external addresses with repair addresses programmed therein; a normal decoder control unit for controlling a turned-on or turned-off state of the normal decoding unit by receiving the external addresses, the signal produced from the repair detecting unit, and a repair signal produced from the repair address determining unit; an address delay unit for controlling delays of the external addresses, based on the output signals of the repair detecting unit; and a sense amplifier control unit driven by an output signal from the address delay unit.

摘要翻译： 公开了一种半导体存储器件的修复电路，包括用于接收和处理外部地址的地址输入单元; 修复检测单元，用于检测是否存在以编程数据为基础修复的地址; 用于选择正常字线的正常解码单元; 用于选择冗余字线的冗余解码单元; 修复地址确定单元，由修复检测单元产生的信号使能，用于将外部地址与其中编程的维修地址进行比较; 正常解码器控制单元，用于通过接收外部地址，从修复检测单元产生的信号和从修复地址确定单元产生的修复信号来控制正常解码单元的导通或关闭状态; 地址延迟单元，用于根据修复检测单元的输出信号来控制外部地址的延迟; 以及由来自地址延迟单元的输出信号驱动的读出放大器控制单元。

公开(公告)号：US07876617B2

公开(公告)日：2011-01-25

申请号：US12325364

申请日：2008-12-01

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G11C16/04

CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C2211/4067

摘要： An apparatus for applying power in a semiconductor memory device includes a first power pin for receiving a first power at a first voltage from an external device, a second power pin for receiving a second power at the first voltage, a memory array block connected to the first power pin, the memory array block writing input data, outputting read data, and refreshing regularly to sustain stored data, a peripheral logic block connected to the first power pin for receiving the first power and communicating with the memory array block to perform data write and read operations, a data output driver connected to the second power pin and driving a data output pin, and a switch for electrically connecting the first power pin and the second power pin by performing a switching operation during a refresh operation of the memory array block.

摘要翻译： 一种用于在半导体存储器件中施加电力的设备包括：第一电源管脚，用于从外部设备接收第一电压的第一电力;第二电源管脚，用于在第一电压下接收第二电力;存储器阵列块， 第一电源引脚，存储器阵列块写入输入数据，输出读取数据和定期刷新以维持存储的数据;连接到第一电源引脚的外围逻辑块，用于接收第一电力并与存储器阵列块通信以执行数据写入 读取操作，连接到第二电源引脚并驱动数据输出引脚的数据输出驱动器和用于通过在存储器阵列块的刷新操作期间执行切换操作来电连接第一电源引脚和第二电源引脚的开关 。

公开(公告)号：US07859880B2

公开(公告)日：2010-12-28

申请号：US12167090

申请日：2008-07-02

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G06F13/00

CPC分类号： G11C11/4085 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/4097

摘要： A semiconductor memory apparatus includes a first memory cell region including a plurality memory cells; a second memory cell region including a plurality memory cells, the second memory cell region positioned adjacent to the first memory cell region; a sub-local data bus coupled with some of the plurality of memory cells in each of the first and second memory cell regions, the sub-local data bus configured to execute data I/O operations of the first and second memory cell regions; a data bus region disposed between the first and second memory cell regions; a first local data bus disposed within the data bus region and configured to execute data I/O operations in conjunction with the sub-local data bus and a first data I/O sense amplifier; and a second local data bus also disposed within the data bus region and also configured to execute data I/O operations in conjunction with the sub-local data bus and a second data I/O sense amplifier.

摘要翻译： 半导体存储装置包括：包括多个存储单元的第一存储单元区域; 包括多个存储单元的第二存储单元区域，位于第一存储单元区域附近的第二存储单元区域; 与第一和第二存储单元区域中的每一个中的多个存储器单元中的一些存储单元耦合的子局部数据总线，被配置为执行第一和第二存储单元区域的数据I / O操作的子局部数据总线; 设置在第一和第二存储单元区域之间的数据总线区域; 布置在所述数据总线区域内并配置为与所述子局部数据总线和第一数据I / O读出放大器一起执行数据I / O操作的第一局部数据总线; 以及第二本地数据总线，其也设置在所述数据总线区域内，并且还被配置为与所述子局部数据总线和第二数据I / O读出放大器一起执行数据I / O操作。

公开(公告)号：US20080315927A1

公开(公告)日：2008-12-25

申请号：US11966300

申请日：2007-12-28

申请人： Kwang Jun Cho ,  Jun Hyun Chun

发明人： Kwang Jun Cho ,  Jun Hyun Chun

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.

摘要翻译： 一种频率调整装置，包括：频率控制信号生成部，其响应于基准时钟信号，生成逐位变化的多位频率控制信号;以及频率调整部，其调整基准的频率 响应于多位频率控制信号的时钟信号。

公开(公告)号：US07355448B2

公开(公告)日：2008-04-08

申请号：US11176394

申请日：2005-07-08

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K17/164

摘要： Provided is a semiconductor memory device that is capable of internally controlling a strength of an output driver. The semiconductor memory device includes: an OCD (off chip driver) control signal generator for decoding EMRS and addresses to generate a plurality of external strength control signals or an internal driving signal; a self control signal generator for detecting a level of a driving voltage to generate a plurality of internal strength control signals in response to the internal driving signal; a control signal generator for generating a strength control signal in response to the external strength control signals or the internal strength control signals; and a data output driver for outputting data, the strength of the data output driver being controlled according to the strength control signal.