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公开(公告)号：US06958936B2
公开(公告)日：2005-10-25
申请号：US10671847
申请日：2003-09-25
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/3418
摘要： The present invention presents a non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process. For a set of storage elements formed over a common well structure, all word-lines are initially charged with the same high voltage erase signal that charges the well to insure there is no net voltage difference between the well and word-lines. The selected word-lines are then discharged to ground while the non-selected word-lines and the well are maintained at the high voltage. According to another aspect of the present invention, this can be accomplished without increasing any pitch area circuit or adding new wires in the memory array, and at minimal additional peripheral area. Advantages include less potential erase disturb in the non-selected storage elements and a tighter erase distribution for the selected elements.
摘要翻译： 本发明提供一种用于其操作的非易失性存储器和方法，其可以在擦除处理期间减少未选择的单元的干扰量。 对于在公共阱结构上形成的一组存储元件，所有字线最初都以相同的高电压擦除信号充电，以确保阱和字线之间没有净电压差。 所选择的字线然后放电到地，而未选择的字线和阱保持在高电压。 根据本发明的另一方面，这可以在不增加任何音调区域电路或在存储器阵列中添加新的线以及在最小额外周边区域的情况下实现。 优点包括在未选择的存储元件中较少的电位擦除干扰以及所选元件的更严格的擦除分布。
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22.发明授权Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells 有权用于减少相邻行存储单元的存储元件之间的耦合效应的技术公开(公告)号：US06781877B2
公开(公告)日：2004-08-24
申请号：US10237426
申请日：2002-09-06
申请人： Raul-Adrian Cernea , Khandker N. Quader , Yan Li , Jian Chen , Yupin Fong
发明人： Raul-Adrian Cernea , Khandker N. Quader , Yan Li , Jian Chen , Yupin Fong
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418
摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.
摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。
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公开(公告)号：US06522580B2
公开(公告)日：2003-02-18
申请号：US09893277
申请日：2001-06-27
申请人： Jian Chen , Tomoharu Tanaka , Yupin Fong , Khandker N. Quader
发明人： Jian Chen , Tomoharu Tanaka , Yupin Fong , Khandker N. Quader
IPC分类号： G11C1634
CPC分类号： G11C11/5628 , G11C11/5621 , G11C16/0483 , G11C16/12 , G11C16/3404 , G11C16/3418 , G11C16/3454 , G11C16/3459
摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.
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公开(公告)号：US06396757B1
公开(公告)日：2002-05-28
申请号：US09912136
申请日：2001-07-24
IPC分类号： G11C702
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C2211/5634 , G11C2211/5645
摘要： A multiple output current mirror of improved accuracy suitable for use in a multi-level memory or analog applications is described. A reference current is mirrored in number of branches to produce replicas of the original current without degrading the original current. Both the mirrored transistor, through which the original current flows, and the mirroring transistors, which provide the replicated currents in each of the branches, are subdivided into a number of separate transistors. The effective channel width of a corresponding original transistor is shared among the transistors forming its subdivision. These subdivided elements are then physically arranged into a number partial current mirrors whose outputs are combined to form the total current mirror. By altering the physical arrangement of the pieces from one partial mirror to the next, variations in operating characteristics and manufacturing processes that are dependent upon positions are reduced since the variation in one partial mirror offsets that in another partial mirror. In an exemplary embodiment, the mirrored element, producing the reference current, and the mirroring elements in each of k branches are each composed of N transistors with a width w, giving an effective width W=Nw for each element and consequently a mirroring ration of 1 for all the branches. All of these N(k+1) transistors are physical placed in a linear arrangement of N partial current mirrors of (k+1) transistors each, where each partial mirror contains a transistor supplying part of the mirrored current and one transistor from each of the k branches mirroring it. Each of the N partial mirrors has its (k+1) elements arranged in a different permutation. The N=5, k=3 case is described in some detail.
摘要翻译： 描述了适用于多层存储器或模拟应用的改进精度的多输出电流镜。 参考电流以分支数量进行镜像，以产生原始电流的副本，而不会降低原始电流。 原始电流流过的镜像晶体管和在每个分支中提供复制电流的镜像晶体管都被细分为多个独立的晶体管。 相应的原始晶体管的有效沟道宽度在形成其细分的晶体管中共享。 然后将这些细分的元件物理地排列成多个部分电流镜，其输出被组合以形成总电流镜。 通过将件从一个局部反射镜改变到下一个部分反射镜的物理布置，减少了依赖于位置的操作特性和制造过程的变化，因为一个部分反射镜的变化抵消了另一部分反射镜中的变化。 在示例性实施例中，产生参考电流的镜像元件和k个分支中的每一个中的镜像元件均由具有宽度w的N个晶体管组成，给出每个元素的有效宽度W = Nw，因此， 1为所有分支。 所有这些N（k + 1）个晶体管被物理放置在每个（k + 1）个晶体管的N个部分电流镜的线性布置中，其中每个部分反射镜包含提供部分镜像电流的晶体管， k分支镜像它。 N个部分镜中的每一个具有排列成不同排列的（k + 1）个元件。 详细描述N = 5，k = 3的情况。
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25.发明授权Nonvolatile semiconductor memory device having protection function for each memory block 有权具有每个存储块的保护功能的非易失性半导体存储器件公开(公告)号：US07952925B2
公开(公告)日：2011-05-31
申请号：US12846118
申请日：2010-07-29
申请人： Tomoharu Tanaka , Koichi Kawai , Khandker N Quader
发明人： Tomoharu Tanaka , Koichi Kawai , Khandker N Quader
CPC分类号： G11C16/22
摘要： A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.
摘要翻译： 非易失性半导体存储器件包括由多个存储块，接口，写入电路和读取电路构成的存储单元阵列。 保护标志写入存储器块。 读出保护标志可以通过接口输出到外部设备。 当从接口输入写入命令时，当所选择的存储器块中的保护标志具有第一值并且当保护标志具有第二值时，写入电路执行写入命令，并且不执行写入命令。
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26.发明申请NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING PROTECTION FUNCTION FOR EACH MEMORY BLOCK 有权具有每个存储块的保护功能的非线性半导体存储器件公开(公告)号：US20100296339A1
公开(公告)日：2010-11-25
申请号：US12846118
申请日：2010-07-29
IPC分类号： G11C16/04
CPC分类号： G11C16/22
摘要： A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.
摘要翻译： 非易失性半导体存储器件包括由多个存储块，接口，写入电路和读取电路构成的存储单元阵列。 保护标志写入存储器块。 读出保护标志可以通过接口输出到外部设备。 当从接口输入写入命令时，当所选择的存储器块中的保护标志具有第一值并且当保护标志具有第二值时，写入电路执行写入命令，并且不执行写入命令。
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27.发明申请NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING PROTECTION FUNCTION FOR EACH MEMORY BLOCK 有权具有每个存储块的保护功能的非线性半导体存储器件公开(公告)号：US20080205143A1
公开(公告)日：2008-08-28
申请号：US12108272
申请日：2008-04-23
CPC分类号： G11C16/22
摘要： A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.
摘要翻译： 非易失性半导体存储器件包括由多个存储块，接口，写入电路和读取电路构成的存储单元阵列。 保护标志写入存储器块。 读出保护标志可以通过接口输出到外部设备。 当从接口输入写入命令时，当所选择的存储器块中的保护标志具有第一值并且当保护标志具有第二值时，写入电路执行写入命令，并且不执行写入命令。
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公开(公告)号：US07379346B2
公开(公告)日：2008-05-27
申请号：US11223055
申请日：2005-09-08
IPC分类号： G11C11/03
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/3418
摘要： A non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process are presented. For a set of storage elements formed over a common well structure, all word-lines are initially charged with the same high voltage erase signal that charges the well to insure there is no net voltage difference between the well and word-lines. The selected word-lines are then discharged to ground while the non-selected word-lines and the well are maintained at the high voltage. This can be accomplished without increasing any pitch area circuit or adding new wires in the memory array, and at minimal additional peripheral area. Advantages include less potential erase disturb in the non-selected storage elements and a tighter erase distribution for the selected elements.
摘要翻译： 提出了一种用于其操作的非易失性存储器和方法，其可以在擦除处理期间减少未选择的单元的干扰量。 对于在公共阱结构上形成的一组存储元件，所有字线最初都以相同的高电压擦除信号充电，以确保阱和字线之间没有净电压差。 所选择的字线然后放电到地，而未选择的字线和阱保持在高电压。 这可以在不增加任何音调区域电路或在存储器阵列中添加新的线以及在最小额外的外围区域的情况下实现。 优点包括在未选择的存储元件中较少的电位擦除干扰以及所选元件的更严格的擦除分布。
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29.发明授权Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states 有权用于减少在多个数据状态下操作的非易失性存储器的存储元件之间的耦合效应的操作技术公开(公告)号：US07224613B2
公开(公告)日：2007-05-29
申请号：US11205595
申请日：2005-08-16
申请人： Jian Chen , Tomoharu Tanaka , Yupin Fong , Khandker N. Quader
发明人： Jian Chen , Tomoharu Tanaka , Yupin Fong , Khandker N. Quader
IPC分类号： G11C16/34
CPC分类号： G11C11/5628 , G11C11/5621 , G11C16/0483 , G11C16/12 , G11C16/3404 , G11C16/3418 , G11C16/3454 , G11C16/3459
摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.
摘要翻译： 具有每个具有至少一个存储元件的存储器单元阵列的非易失性存储器系统每个存储元件具有多个存储级别范围。 闪存电可擦除和可编程只读存储器（EEPROM）是示例，其中存储元件是电浮动栅极。 操作存储器以通过在相邻单元被编程之后第二次编程一些单元来最小化耦合在相邻浮动栅极之间的电荷的影响。 第二编程步骤还压缩至少一些编程状态下的电荷水平分布。 这增加了状态之间的分离和/或允许在给定的存储窗口内包含更多的状态。 所描述的实现方案是用于NAND型闪存EEPROM。
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公开(公告)号：US07095654B2
公开(公告)日：2006-08-22
申请号：US11223709
申请日：2005-09-09
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3486
摘要： A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.
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