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    Method for programming non-volatile memory with reduced bit line interference and associated device
    4.
    发明授权
    Method for programming non-volatile memory with reduced bit line interference and associated device 有权
    用于减少位线干扰和相关设备的非易失性存储器编程方法

    公开(公告)号：US09437319B1

    公开(公告)日：2016-09-06

    申请号：US14750065

    申请日：2015-06-25

    申请人： Macronix International Co., Ltd.

    发明人： Atsuhiro Suzuki ,  Ya Jui Lee ,  Kuan Fu Chen ,  Chih-Wei Lee

    IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

    CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459 ,  G11C16/3481 ,  G11C16/3486

    摘要： Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a non-volatile memory device comprising a set of cells, each cell associated with a bit line; shooting a programming voltage across each cell; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based at least in part on the detected threshold voltage for each cell; and shooting the programming voltage until the threshold voltage for each cell is greater than a verify voltage. For each shot a fast bit line bias is applied to the bit line associated each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.

    摘要翻译： 提供了在编程非易失性存储器时减少位线干扰的方法，装置和/或类似装置。 一种方法包括提供包括一组单元的非易失性存储器件，每个单元与位线相关联; 拍摄每个单元格上的编程电压; 检测每个单元的阈值电压; 至少部分地基于每个单元的检测到的阈值电压来识别该组单元的快速子集和该组单元的慢子集; 并拍摄编程电压，直到每个单元的阈值电压大于验证电压。 对于每个镜头，快速位线偏置被施加到与快速子集的每个单元相关联的位线，并且慢位线偏置被施加到与慢子集的每个单元相关联的位线。

    Non-volatile Memory Program Algorithm Device And Method
    7.
    发明申请
    Non-volatile Memory Program Algorithm Device And Method 有权
    非易失性存储器程序算法设备与方法

    公开(公告)号：US20140269058A1

    公开(公告)日：2014-09-18

    申请号：US14214097

    申请日：2014-03-14

    申请人： Silicon Storage Technology, Inc.

    发明人： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

    IPC分类号： G11C16/34 ,  G11C16/12

    CPC分类号： G11C16/3486 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

    摘要： A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

    摘要翻译： 一种用于使用编程电压的重复脉冲编程单元的非易失性存储器件和方法，具有交错读取操作以确定读取电流的电平，直到达到期望的编程状态。 每个连续的编程脉冲具有相对于先前脉冲增加阶跃值的一个或多个编程电压。 对于单级单元类型，在达到第一读取电流阈值之后，每个单元从编程脉冲中单独地移除，并且此后的一个或多个猝发脉冲的步长值增加。 对于多级单元类型，步长值在其中一个单元达到第一读取电流阈值后下降，一些单元在达到第二读取电流阈值之后单独地从编程脉冲中移除，而其他单元在编程脉冲之后被单独从编程脉冲中移除 达到第三个读取电流阈值。

    Nonvolatile memory cell with well extending under transistor and data storage capacitor of memory cell
    8.
    发明授权
    Nonvolatile memory cell with well extending under transistor and data storage capacitor of memory cell 有权
    非易失性存储单元在存储器单元的晶体管和数据存储电容器下具有良好的扩展

    公开(公告)号：US08456910B2

    公开(公告)日：2013-06-04

    申请号：US12846996

    申请日：2010-07-30

    申请人： Dzianis Lukashevich

    发明人： Dzianis Lukashevich

    IPC分类号： G11C14/00

    CPC分类号： H01L21/28273 ,  G11C16/0433 ,  G11C16/3486 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

    摘要： One embodiment relates to a memory device. The memory device includes a capacitor having a first capacitor plate and a second capacitor plate, wherein the first and second capacitor plates are separated by an insulating layer and are formed over a first portion of a semiconductor substrate. The memory device also includes a transistor having a source region, a drain region, and a gate region, where the gate region is coupled to the second capacitor plate. The transistor is formed over a second portion of the semiconductor substrate. A well region is disposed in the first and second portions of the semiconductor substrate and has a doping-type that is opposite a doping-type of the semiconductor substrate. Other embodiments are also disclosed.

    摘要翻译： 一个实施例涉及存储器件。 存储器件包括具有第一电容器板和第二电容器板的电容器，其中第一和第二电容器板被绝缘层隔开并形成在半导体衬底的第一部分之上。 存储器件还包括具有源极区，漏极区和栅极区的晶体管，其中栅极区耦合到第二电容器板。 晶体管形成在半导体衬底的第二部分上。 阱区设置在半导体衬底的第一和第二部分中，并且具有与半导体衬底的掺杂型相反的掺杂型。 还公开了其他实施例。

    Programming non-volatile memory with variable initial programming pulse
    9.
    发明授权
    Programming non-volatile memory with variable initial programming pulse 有权
    用可变的初始编程脉冲编程非易失性存储器

    公开(公告)号：US08254177B2

    公开(公告)日：2012-08-28

    申请号：US12427007

    申请日：2009-04-21

    申请人： Gerrit Jan Hemink

    发明人： Gerrit Jan Hemink

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3468 ,  G11C16/3486 ,  G11C2211/5621 ,  G11C2211/5648

    摘要： Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of the non-volatile storage elements to a set of target conditions using programming pulses. For at least a subset of the programming processes, a programming pulse associated with achieving an intermediate result for a respective programming process is identified, a pulse increment between programming pulses is decreased for the respective programming process while continuing the respective programming process to program non-volatile storage elements to the respective one or more targets and the identified programming pulse is used to adjust a starting programming voltage for a subsequent programming process.

    摘要翻译： 对多个非易失性存储元件执行多个编程处理。 编程过程中的每一个操作以使用编程脉冲将至少一个非易失性存储元件的子集编程为一组目标条件。 对于编程过程的至少一个子集，识别与实现相应编程处理的中间结果相关联的编程脉冲，针对相应的编程过程减少编程脉冲之间的脉冲增量，同时继续相应的编程处理， 易失性存储元件到相应的一个或多个目标，并且所识别的编程脉冲用于调整用于后续编程处理的起始编程电压。

    PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE
    10.
    发明申请
    PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE 有权
    编程具有高分辨率可变初始编程脉冲的非易失性存储器

    公开(公告)号：US20120039121A1

    公开(公告)日：2012-02-16

    申请号：US13237755

    申请日：2011-09-20

    申请人： Gerrit Jan Hemink

    发明人： Gerrit Jan Hemink

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3468 ,  G11C16/3486 ,  G11C2211/5621 ,  G11C2211/5648

    摘要： Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result. Subsequent programming process are adjusted based on the identification of the program pulse if the one or more sensing operations determined that less than a required number of non-volatile storage elements achieved any of the alternative results.

    摘要翻译： 编程过程中的每一个都使用编程脉冲来操作至少一个非易失性存储元件的子集到相应的目标条件集合。 编程过程的至少一个子集包括识别与实现相应编程处理的特定结果相关联的编程脉冲，并且以非易失性存储元件的一个或多个替代结果执行一个或多个感测操作。 如果一个或多个感测操作确定大于预定数量的非易失性存储元件实现了第一替代结果，则基于第一备选结果和编程脉冲的识别来调整后续编程处理。 如果一个或多个感测操作确定小于所需数量的非易失性存储元件实现任何替代结果，则基于编程脉冲的识别来调整后续编程处理。