公开(公告)号：US08111551B2

公开(公告)日：2012-02-07

申请号：US13099024

申请日：2011-05-02

申请人： Tomoharu Tanaka ,  Koichi Kawai ,  Khandker N Quader

发明人： Tomoharu Tanaka ,  Koichi Kawai ,  Khandker N Quader

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C16/22

摘要： A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

摘要翻译： 非易失性半导体存储器件包括由多个存储块，接口，写入电路和读取电路构成的存储单元阵列。 保护标志写入存储器块。 读出保护标志可以通过接口输出到外部设备。 当从接口输入写入命令时，当所选择的存储器块中的保护标志具有第一值并且当保护标志具有第二值时，写入电路执行写入命令，并且不执行写入命令。

公开(公告)号：US07420846B2

公开(公告)日：2008-09-02

申请号：US10552948

申请日：2004-04-08

申请人： Jian Chen ,  Khandker N. Quader

发明人： Jian Chen ,  Khandker N. Quader

IPC分类号： G11C16/06

CPC分类号： G11C7/04 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/20 ,  G11C16/26 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifting according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.

摘要翻译： 在非易失性存储器中，用于区分由负阈值电压表征的数据状态的读取参数与由正阈值电压表征的数据状态进行补偿，而不是硬连线到地。 在示例性实施例中，对于具有高于地面的最低阈值的数据状态的读取参数被温度补偿以反映存储元件群在读取参数的任一侧上的偏移。 根据另一方面，提出了可以利用操作条件补偿的感测参数的擦除过程。 由于感测参数不再固定为对应于0伏的值，而是根据工作条件进行移位，即使在降低的工作电压下，也为各种擦除验证电平提供足够的余量。

公开(公告)号：US06839281B2

公开(公告)日：2005-01-04

申请号：US10414132

申请日：2003-04-14

申请人： Jian Chen ,  Khandker N. Quader

发明人： Jian Chen ,  Khandker N. Quader

IPC分类号： G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C7/04 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/20 ,  G11C16/26 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifling according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.

摘要翻译： 在非易失性存储器中，用于区分由负阈值电压表征的数据状态的读取参数与由正阈值电压表征的数据状态进行补偿，而不是硬连线到地。 在示例性实施例中，对于具有高于地面的最低阈值的数据状态的读取参数被温度补偿以反映存储元件群在读取参数的任一侧上的偏移。 根据另一方面，提出了可以利用操作条件补偿的感测参数的擦除过程。 由于感测参数不再固定在对应于0伏的值，而是根据工作条件进行移位，即使在降低的工作电压下，也为各种擦除验证电平提供足够的余量。

公开(公告)号：US06696880B2

公开(公告)日：2004-02-24

申请号：US10014161

申请日：2001-11-09

申请人： Feng Pan ,  Khandker N. Quader

发明人： Feng Pan ,  Khandker N. Quader

IPC分类号： H03K1716

CPC分类号： G11C5/145 ,  H03K17/063

摘要： The invention utilizes a boost-strap method to improve switch operation in a design that is particularly advantageous for supplying high voltages within a low voltage design. A native NMOS transistor, a PMOS transistor, and a capacitor are connected in series between the high voltage source and the output, where the gate of the native NMOS is connect to the output. In an initialization phase, the plate of the capacitor connected to the output is precharged by receiving the input signal while the other plate of the capacitor is held near ground. In a subsequent enable phase, the native NMOS and PMOS transistors are turned on and the high voltage is supplied to the output.

摘要翻译： 本发明利用升压带方法来改进对于在低电压设计中提供高电压特别有利的设计中的开关操作。 天线NMOS晶体管，PMOS晶体管和电容器串联连接在高电压源和输出端之间，其中天线NMOS的栅极连接到输出端。 在初始化阶段，连接到输出端的电容器的板通过接收输入信号而被预充电，而电容器的另一个板保持靠近地。 在随后的使能阶段，天线NMOS和PMOS晶体管导通，高压被提供给输出。

公开(公告)号：US5243700A

公开(公告)日：1993-09-07

申请号：US898190

申请日：1992-06-12

申请人： Robert E. Larsen ,  Khandker N. Quader ,  Joseph H. Salmon ,  Terry L. Kendall

发明人： Robert E. Larsen ,  Khandker N. Quader ,  Joseph H. Salmon ,  Terry L. Kendall

IPC分类号： G06F13/12

CPC分类号： G06F13/126

摘要： A port expander for providing an external memory to be used with a microcontroller but recapturing the use of I/O ports which are lost due to the coupling of the memory. Two ports are coupled to the microcontroller for transfer of address and data information. An EPROM in the port expander provides the external memory while a special function register is used to couple data to and from two I/O ports. A configuration register provides programmability of which address values address the memory and which address values address the special function registers.

摘要翻译： 一种端口扩展器，用于提供要与微控制器一起使用的外部存储器，但是重新捕获由于存储器的耦合而丢失的I / O端口的使用。 两个端口耦合到微控制器以传送地址和数据信息。 端口扩展器中的EPROM提供外部存储器，而使用特殊功能寄存器将数据耦合到两个I / O端口和从两个I / O端口耦合数据。 配置寄存器提供哪些地址值可寻址存储器的可编程性，哪些地址值用于寻址特殊功能寄存器。

公开(公告)号：US5077738A

公开(公告)日：1991-12-31

申请号：US707241

申请日：1991-05-22

申请人： Robert E. Larsen ,  Khandker N. Quader ,  Joseph H. Salmon

发明人： Robert E. Larsen ,  Khandker N. Quader ,  Joseph H. Salmon

IPC分类号： G11C29/46

CPC分类号： G11C29/46

摘要： A test mode enable circuit in which a test mode code is written to one latch and a test mode enable code is written to a second latch. The test mode enable code is compared to preprogrammed values stored in the enable circuit. When the test mode enable code matches the preprogrammed value, a presence of a high voltage activates a test mode enable signal for entering the test mode. The latched test mode code is then used to perform the desired test. Additionally a pulsewidth detector is used as a filter to permit only high voltages of a minimum pulsewidth duration to activate the enable signal thereby preventing false triggering.

摘要翻译： 一种测试模式使能电路，其中将测试模式代码写入一个锁存器，并将测试模式使能代码写入第二个锁存器。 将测试模式使能代码与存储在使能电路中的预编程值进行比较。 当测试模式使能代码与预编程值匹配时，高电压的存在激活测试模式使能信号以进入测试模式。 然后使用锁存的测试模式代码执行所需的测试。 此外，脉冲宽度检测器被用作滤波器，以仅允许最小脉冲宽度持续时间的高电压来激活使能信号从而防止错误触发。

公开(公告)号：US07468915B2

公开(公告)日：2008-12-23

申请号：US11538521

申请日：2006-10-04

申请人： Daniel C. Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker N. Quader

发明人： Daniel C. Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker N. Quader

IPC分类号： G11C11/34

CPC分类号： G11C7/12 ,  G11C16/12 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1204

摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

摘要翻译： 在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。 提出了减少这些电流的技术。 在第一方面，减少了在字线上同时编程的单元的数量。 在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。 多个单元可以并行编程，但是它们被布置成处于分开的平面中。 这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合 这些。 在第二个互补方面，位线上的电压电平改变的速率是可调节的。 通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。 这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

公开(公告)号：US07376010B2

公开(公告)日：2008-05-20

申请号：US11387818

申请日：2006-03-24

申请人： Tomoharu Tanaka ,  Koichi Kawai ,  Khandker N. Quader

发明人： Tomoharu Tanaka ,  Koichi Kawai ,  Khandker N. Quader

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C16/22

摘要： A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

摘要翻译： 非易失性半导体存储器件包括由多个存储块，接口，写入电路和读取电路构成的存储单元阵列。 保护标志写入存储器块。 读出保护标志可以通过接口输出到外部设备。 当从接口输入写入命令时，当所选择的存储器块中的保护标志具有第一值并且当保护标志具有第二值时，写入电路执行写入命令，并且不执行写入命令。

公开(公告)号：US07061798B2

公开(公告)日：2006-06-13

申请号：US10966451

申请日：2004-10-15

申请人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

发明人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

IPC分类号： G11C16/34

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

公开(公告)号：US07046548B2

公开(公告)日：2006-05-16

申请号：US11055776

申请日：2005-02-09

申请人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。