公开(公告)号：US08349690B2

公开(公告)日：2013-01-08

申请号：US12649999

申请日：2009-12-30

Applicant: Jin-Ku Lee ,  Young-Ho Lee ,  Mi-Ri Lee

Inventor： Jin-Ku Lee ,  Young-Ho Lee ,  Mi-Ri Lee

IPC: H01L21/336

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7856

Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

公开(公告)号：US20120302047A1

公开(公告)日：2012-11-29

申请号：US13230931

申请日：2011-09-13

Applicant: Mi-Ri LEE ,  Jae-Geun Oh ,  Seung-Joon Jeon ,  Jin-Ku Lee ,  Bong-Seok Jeon

Inventor： Mi-Ri LEE ,  Jae-Geun Oh ,  Seung-Joon Jeon ,  Jin-Ku Lee ,  Bong-Seok Jeon

IPC: H01L21/265

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for fabricating a semiconductor device includes forming a structure having first surfaces at a height above a second surface, which is provided between the first surfaces, forming a first silicon layer on the structure, performing a tilt ion implantation process on the first silicon layer to form a crystalline region and an amorphous region, forming a second silicon layer on the amorphous region, removing the second silicon layer and the first silicon layer until a part of the second surface is exposed, thereby forming an etch barrier, and etching using the etch barrier to form an open part that exposes a part of a sidewall of the structure.

Abstract translation: 一种半导体器件的制造方法，其特征在于，在所述第一面之间形成具有位于第二面以上的高度的第一表面的结构，在所述结构上形成第一硅层，对所述第一硅层进行倾斜离子注入工序 以形成晶体区域和非晶区域，在非晶区域上形成第二硅层，去除第二硅层和第一硅层，直到第二表面的一部分露出，从而形成蚀刻阻挡层，并使用 蚀刻阻挡层以形成暴露结构的侧壁的一部分的开放部分。

公开(公告)号：US20110212591A1

公开(公告)日：2011-09-01

申请号：US12964562

申请日：2010-12-09

Applicant: Jae-Geun OH ,  Young-Ho Lee ,  Jin-Ku Lee ,  Mi-Ri Lee

Inventor： Jae-Geun OH ,  Young-Ho Lee ,  Jin-Ku Lee ,  Mi-Ri Lee

IPC: H01L21/336 ,  H01L21/265

CPC classification number: H01L21/324 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/28061 ,  H01L29/66575

Abstract: A method for fabricating a transistor of a semiconductor device includes: forming a gate pattern over a substrate; forming a junction region by performing an on implantation process onto the substrate at opposite sides of the gate pattern; performing a solid phase epitaxial (SPE) process on the junction region at a temperature approximately ranging from 770° C. to 850° C.; and performing a rapid thermal annealing (RTA) process on the junction region.

Abstract translation: 一种制造半导体器件的晶体管的方法包括：在衬底上形成栅极图案; 通过在所述栅极图案的相对侧上对所述衬底进行注入工艺来形成结区域; 在大约770℃至850℃的温度下在接合区域进行固相外延（SPE）工艺; 并在接合区域上进行快速热退火（RTA）处理。

公开(公告)号：US20110189843A1

公开(公告)日：2011-08-04

申请号：US12774311

申请日：2010-05-05

Applicant: Jin-Ku Lee ,  Jae-Geun Oh ,  Young-Ho Lee ,  Mi-Ri Lee ,  Seung-Beom Baek

Inventor： Jin-Ku Lee ,  Jae-Geun Oh ,  Young-Ho Lee ,  Mi-Ri Lee ,  Seung-Beom Baek

IPC: H01L21/306

CPC classification number: H01L29/66575 ,  H01L21/306

Abstract: A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.

Abstract translation: 在三维（3D）导电结构的期望位置处形成掺杂区域的掺杂方法相对容易地控制掺杂深度和掺杂区域的掺杂剂量，具有浅掺杂深度，并且防止浮体效应。 使用相同的掺杂方法制造半导体器件。 该方法包括：形成具有侧壁的导电结构，暴露导电结构的侧壁的一部分，以及通过执行等离子体掺杂工艺在侧壁的暴露部分中形成掺杂区域。

公开(公告)号：US20090163013A1

公开(公告)日：2009-06-25

申请号：US12131558

申请日：2008-06-02

Applicant: Seok Pyo Song ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Ki Seon Park ,  Sun Hwan Hwang ,  Mi Ri Lee ,  Gil Jae Park

Inventor： Seok Pyo Song ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Ki Seon Park ,  Sun Hwan Hwang ,  Mi Ri Lee ,  Gil Jae Park

IPC: H01L21/28

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/11521

Abstract: Provided is a method for forming a gate of a non-volatile memory device. A tunneling layer, a charge trapping layer, a blocking layer, and a control gate layer are formed on a semiconductor substrate. A hard mask is formed on the control gate layer. The hard mask defines a region on which a gate is formed. A gate pattern is formed by etching the control gate layer, the blocking layer, the charge trapping layer, and the tunneling layer. A damage compensation layer on a side of the gate pattern is formed using ultra low pressure plasma of a pressure range from approximately 1 mT to approximately 100 mT.

Abstract translation: 提供了一种用于形成非易失性存储器件的栅极的方法。 在半导体衬底上形成隧道层，电荷俘获层，阻挡层和控制栅极层。 在控制栅极层上形成硬掩膜。 硬掩模限定形成栅极的区域。 通过蚀刻控制栅极层，阻挡层，电荷俘获层和隧道层形成栅极图案。 使用压力范围为约1mT至约100mT的超低压等离子体形成栅极图案侧的损伤补偿层。

公开(公告)号：USD584753S1

公开(公告)日：2009-01-13

申请号：US29289570

申请日：2007-07-25

Applicant: Yeon Moo Chung ,  Harata Tomohiro ,  Mi Ri Lee

Designer： Yeon Moo Chung ,  Harata Tomohiro ,  Mi Ri Lee

公开(公告)号：USD574739S1

公开(公告)日：2008-08-12

申请号：US29293972

申请日：2007-12-19

Applicant: Mi-Ri Lee ,  Sung-Won Park

Designer： Mi-Ri Lee ,  Sung-Won Park

公开(公告)号：US20060020632A1

公开(公告)日：2006-01-26

申请号：US11184838

申请日：2005-07-20

Applicant: Boung-Il Choi ,  Je-Eung Park ,  Mi-Ri Lee

Inventor： Boung-Il Choi ,  Je-Eung Park ,  Mi-Ri Lee

IPC: G06F17/00

CPC classification number: G06Q10/10

Abstract: A method of increasing productivity in an organization by sharing praise, encouragement, recognition, and gratitude among members of the organization, wherein the method also provides virtual space for the members to exchange and share inspirational messages.

Abstract translation: 通过在组织成员之间分享赞美，鼓励，认可和感激，提高组织生产率的方法，其中该方法还为成员交换和分享鼓舞人心的消息提供虚拟空间。