公开(公告)号：US20090163013A1

公开(公告)日：2009-06-25

申请号：US12131558

申请日：2008-06-02

申请人： Seok Pyo Song ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Ki Seon Park ,  Sun Hwan Hwang ,  Mi Ri Lee ,  Gil Jae Park

发明人： Seok Pyo Song ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Ki Seon Park ,  Sun Hwan Hwang ,  Mi Ri Lee ,  Gil Jae Park

IPC分类号： H01L21/28

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： Provided is a method for forming a gate of a non-volatile memory device. A tunneling layer, a charge trapping layer, a blocking layer, and a control gate layer are formed on a semiconductor substrate. A hard mask is formed on the control gate layer. The hard mask defines a region on which a gate is formed. A gate pattern is formed by etching the control gate layer, the blocking layer, the charge trapping layer, and the tunneling layer. A damage compensation layer on a side of the gate pattern is formed using ultra low pressure plasma of a pressure range from approximately 1 mT to approximately 100 mT.

摘要翻译： 提供了一种用于形成非易失性存储器件的栅极的方法。 在半导体衬底上形成隧道层，电荷俘获层，阻挡层和控制栅极层。 在控制栅极层上形成硬掩膜。 硬掩模限定形成栅极的区域。 通过蚀刻控制栅极层，阻挡层，电荷俘获层和隧道层形成栅极图案。 使用压力范围为约1mT至约100mT的超低压等离子体形成栅极图案侧的损伤补偿层。

公开(公告)号：US08735962B2

公开(公告)日：2014-05-27

申请号：US13599680

申请日：2012-08-30

申请人： Sung Jin Whang ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Min Soo Kim

发明人： Sung Jin Whang ,  Dong Sun Sheen ,  Seung Ho Pyi ,  Min Soo Kim

IPC分类号： H01L29/788 ,  H01L21/20

CPC分类号： H01L27/11556 ,  H01L29/7889

摘要： A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.

摘要翻译： 根据本发明的实施例的半导体器件包括从半导体衬底向上突出的垂直沟道层，覆盖垂直沟道层的侧壁的隧道绝缘层，彼此分离并堆叠的多个浮动栅极 沿着垂直沟道层，并且在其间插入隧道绝缘层的周围的垂直沟道层，分别包围多个浮置栅极的多个控制栅极和设置在多个控制栅极之间的层间绝缘层。

公开(公告)号：US20090004802A1

公开(公告)日：2009-01-01

申请号：US11966231

申请日：2007-12-28

申请人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Heung Jae Cho ,  Yong Top Kim

发明人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Heung Jae Cho ,  Yong Top Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  Y10S438/942

摘要： A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.

摘要翻译： 一种制造具有电荷捕获层的非易失性存储器件的方法包括在衬底上形成隧道层，电荷俘获层，阻挡层和控制栅电极层，在控制栅电极层上形成掩模层图案 使用掩模层图案作为蚀刻掩模进行蚀刻处理以去除控制栅电极层的暴露部分，其中蚀刻工艺作为过度蚀刻进行，以将电荷捕获层除去指定厚度，形成绝缘层 用于阻止电荷在控制栅电极层和掩模层图案上移动，对绝缘层进行各向异性蚀刻，以在控制栅电极层的侧壁和阻挡层的一部分上侧壁上形成绝缘层图案，以及 对通过各向异性蚀刻暴露的阻挡层进行蚀刻处理，其中执行蚀刻处理 作为过量蚀刻以将电荷捕获层除去指定的厚度。

公开(公告)号：US07981786B2

公开(公告)日：2011-07-19

申请号：US11966231

申请日：2007-12-28

申请人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Heung Jae Cho ,  Yong Top Kim

发明人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Heung Jae Cho ,  Yong Top Kim

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  Y10S438/942

摘要： A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.

摘要翻译： 一种制造具有电荷捕获层的非易失性存储器件的方法包括在衬底上形成隧道层，电荷俘获层，阻挡层和控制栅电极层，在控制栅电极层上形成掩模层图案 使用掩模层图案作为蚀刻掩模进行蚀刻处理以去除控制栅电极层的暴露部分，其中蚀刻工艺作为过度蚀刻进行，以将电荷捕获层除去指定厚度，形成绝缘层 用于阻止电荷在控制栅电极层和掩模层图案上移动，对绝缘层进行各向异性蚀刻，以在控制栅电极层的侧壁和阻挡层的一部分上侧壁上形成绝缘层图案，以及 对通过各向异性蚀刻暴露的阻挡层进行蚀刻处理，其中执行蚀刻处理 作为过量蚀刻以将电荷捕获层除去指定的厚度。

公开(公告)号：US20090163014A1

公开(公告)日：2009-06-25

申请号：US12139623

申请日：2008-06-16

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

IPC分类号： H01L21/28

CPC分类号： H01L21/28282 ,  H01L21/3105 ,  H01L21/31608 ,  H01L21/31616

摘要： A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to the control gate electrode. The blocking layer is densified by allowing the increased temperature to be transferred to the blocking layer contacting the control gate electrode.

摘要翻译： 一种用于制造具有电荷捕获层的非易失性存储器件的方法，其中在半导体衬底上形成有隧道层，电荷俘获层，阻挡层和控制栅电极。 通过向控制栅电极施加磁场来增加控制栅电极的温度。 通过允许将升高的温度转移到与控制栅电极接触的阻挡层而使阻挡层致密化。

公开(公告)号：US07919371B2

公开(公告)日：2011-04-05

申请号：US12139623

申请日：2008-06-16

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/3105 ,  H01L21/31608 ,  H01L21/31616

摘要： A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to the control gate electrode. The blocking layer is densified by allowing the increased temperature to be transferred to the blocking layer contacting the control gate electrode.

摘要翻译： 一种用于制造具有电荷捕获层的非易失性存储器件的方法，其中在半导体衬底上形成有隧道层，电荷俘获层，阻挡层和控制栅电极。 通过向控制栅电极施加磁场来增加控制栅电极的温度。 通过允许将升高的温度转移到与控制栅电极接触的阻挡层而使阻挡层致密化。

公开(公告)号：US20090108334A1

公开(公告)日：2009-04-30

申请号：US12164720

申请日：2008-06-30

申请人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Yong Top Kim ,  Jae Young Park ,  Ki Hong Lee

发明人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Yong Top Kim ,  Jae Young Park ,  Ki Hong Lee

IPC分类号： H01L21/28 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11565 ,  H01L27/11568

摘要： A charge trapping device includes a plurality of isolation layers, a plurality of charge trapping layers, a blocking layer, and a control gate electrode. The isolation layers define active regions, and the isolation layers and active regions extend as respective stripes along a first direction on a semiconductor substrate. The charge trapping layers are disposed on the active regions in island forms where the charge trapping layers are separated from each other in the first direction and disposed on the respective active regions between the isolation layers in a second direction perpendicular to the first direction. The blocking layer is disposed on the isolation layers and the charge trapping layers. The control gate electrode is disposed on the charge trapping layer.

摘要翻译： 电荷俘获装置包括多个隔离层，多个电荷俘获层，阻挡层和控制栅电极。 隔离层限定有源区，并且隔离层和有源区沿着半导体衬底上的第一方向作为相应条延伸。 电荷捕获层以岛形式设置在有源区，其中电荷捕获层在第一方向上彼此分离，并且在垂直于第一方向的第二方向上设置在隔离层之间的相应有源区上。 阻挡层设置在隔离层和电荷俘获层上。 控制栅电极设置在电荷捕获层上。

公开(公告)号：US09755085B2

公开(公告)日：2017-09-05

申请号：US13537650

申请日：2012-06-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

IPC分类号： H01L27/088 ,  H01L21/8239 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582

CPC分类号： H01L27/11582 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

公开(公告)号：US08853767B2

公开(公告)日：2014-10-07

申请号：US13601396

申请日：2012-08-31

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1158 ,  H01L27/11582 ,  H01L27/12 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.

摘要翻译： 半导体器件包括第一源极层; 第二源层中的至少一个，所述第二源极层基本上形成在所述第一源极层中; 基本上层叠在所述第一源极层上的多个导电层; 沟道层，其穿过所述多个导电层并耦合到所述第二源极层; 以及第三源层中的至少一个，所述第三源极层基本上形成在所述第二源极层中，其中所述第三源极层穿过所述第二源极层并且耦合到所述第一源极层。

公开(公告)号：US20130087846A1

公开(公告)日：2013-04-11

申请号：US13598414

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

IPC分类号： H01L21/20 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/32133 ,  H01L29/4234 ,  H01L29/66666 ,  H01L29/66833

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.