公开(公告)号：US07528829B2

公开(公告)日：2009-05-05

申请号：US11346897

申请日：2006-02-03

申请人： Charles N. Boyd ,  Michael A. Toelle

发明人： Charles N. Boyd ,  Michael A. Toelle

IPC分类号： G06T15/00 ,  G06T1/00 ,  G06F15/16 ,  G06F13/14

CPC分类号： G06T1/60

摘要： An API is provided to feed multiple data objects, wherever originated or located at the time of operation, to a 3D graphics chip simultaneously or in parallel. Multiple containers may be fed to a 3D graphics chip memory at the same time. In the case where data is being transmitted to a graphics chip memory, wherein the data includes the same spatial position of pixel(s), but only the orientation or color is changing, the data may be loaded into two separate containers, with a header description understood by the graphics chip and implemented by the graphics API, whereby a single copy of the position data can be loaded into one container, and the changing color or orientation data may be loaded into a second container. Thus, when received by the graphics chip, the data is loaded correctly into register space and processed according to the header description.

公开(公告)号：US20080198169A1

公开(公告)日：2008-08-21

申请号：US12112676

申请日：2008-04-30

申请人： Charles N. Boyd ,  Michele B. Boland ,  Michael A. Toelle ,  Anantha Rao Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen H. Wright

发明人： Charles N. Boyd ,  Michele B. Boland ,  Michael A. Toelle ,  Anantha Rao Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen H. Wright

IPC分类号： G06T1/00

CPC分类号： G06F9/325 ,  G06F9/3842 ,  G06F9/3879 ,  G06T15/005 ,  G06T15/80

摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.

摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

公开(公告)号：US07280111B2

公开(公告)日：2007-10-09

申请号：US10981963

申请日：2004-11-05

申请人： Charles F. Boyd ,  Michael A. Toelle

发明人： Charles F. Boyd ,  Michael A. Toelle

IPC分类号： G09G5/36 ,  G09G5/37 ,  G06F13/00 ,  G06T15/60 ,  G06T15/00

CPC分类号： G06T15/00 ,  G06T15/005 ,  G06T15/80 ,  G06T2210/32

摘要： A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.

摘要翻译： 用于与具有本地寄存器的顶点着色器和像素着色器的硬件实现进行通信的三维API。 关于顶点着色器，提供可以利用片上寄存器索引的API通信，并且也为在寄存器级别片上实现的专用功能提​​供API通信，该专用功能输出片上寄存器索引的小数部分 输入（s）。 对于像素着色器，针对特定功能提供API通信，其在执行线性内插功能的寄存器级别的片上实现，并且还为在寄存器级别片上实现的专用修改器提供API通信， 执行修改功能，包括否定，补充，重新映射，粘贴偏移，缩放和饱和。 有利地，这些API通信将这些非常有用的片上图形算法元件暴露给开发者，同时隐藏来自开发者的顶点着色器和像素着色器芯片的操作的细节。

公开(公告)号：US07023431B2

公开(公告)日：2006-04-04

申请号：US09796899

申请日：2001-03-01

申请人： Charles N. Boyd ,  Michael A. Toelle

发明人： Charles N. Boyd ,  Michael A. Toelle

IPC分类号： G06T15/00 ,  G06F15/16

CPC分类号： G06T1/60

摘要： An API is provided to feed multiple data objects, wherever originated or located at the time of operation, to a 3D graphics chip simultaneously or in parallel. Multiple containers may be fed to a 3D graphics chip memory at the same time. In the case where data is being transmitted to a graphics chip memory, wherein the data includes the same spatial position of pixel(s), but only the orientation or color is changing, the data may be loaded into two separate containers, with a header description understood by the graphics chip and implemented by the graphics API, whereby a single copy of the position data can be loaded into one container, and the changing color or orientation data may be loaded into a second container. Thus, when received by the graphics chip, the data is loaded correctly into register space and processed according to the header description.

公开(公告)号：US06252608B1

公开(公告)日：2001-06-26

申请号：US09178078

申请日：1998-10-22

申请人： John M. Snyder ,  James T. Kajiya ,  Steven A. Gabriel ,  Michael A. Toelle

发明人： John M. Snyder ,  James T. Kajiya ,  Steven A. Gabriel ,  Michael A. Toelle

IPC分类号： G06T1700

CPC分类号： G06T11/001 ,  G06T11/40 ,  G06T13/80 ,  G06T15/005 ,  G06T15/04 ,  G06T15/60

摘要： A system for improved shadowing of images using a multiple pass, depth buffer approach includes rendering a scene from the perspective of a light source to construct a shadow depth map in a rasterization buffer. The system computes depth values for the two nearest geometric primitives to the light source for pixels, and stores these depth values in the rasterization buffer. Once the shadow map is constructed, it is stored in shared memory, where it can be retrieved for subsequent rendering passes. The two depth values for each element in the shadow map can be used in combination with a global bias to eliminate self-shadowing artifacts and avoid artifacts in the terminator region. The system supports linear or higher order filtering of data from the shadow depth map to produce smoother transitions from shadowed and un-shadowed portions of an image. In addition, the system supports the re-use of the shadow map and shadowed images for more than one frame.

摘要翻译： 用于使用多遍深度缓冲器方法改善图像的阴影的系统包括从光源的角度渲染场景以在光栅化缓冲器中构造阴影深度图。 系统为像素的光源计算两个最近几何基元的深度值，并将这些深度值存储在光栅化缓冲区中。 一旦构建了影子映射，它就被存储在共享存储器中，在那里它可以被检索以用于后续渲染过程。 阴影贴图中每个元素的两个深度值可以与全局偏差结合使用，以消除自阴影伪像并避免终止器区域中的伪影。 该系统支持来自阴影深度图的数据的线性或高阶滤波，以从图像的阴影和未遮蔽部分产生更平滑的转换。 此外，该系统支持重复使用阴影贴图和阴影图像多于一个帧。

公开(公告)号：US6008820A

公开(公告)日：1999-12-28

申请号：US675435

申请日：1996-06-27

申请人： Joseph W. Chauvin ,  Steven A. Gabriel ,  Howard Good ,  Kent E. Griffin ,  William Chambers Powell, III ,  George Easton Scott, III ,  Michael A. Toelle ,  John G. Torborg, Jr. ,  James E. Veres

发明人： Joseph W. Chauvin ,  Steven A. Gabriel ,  Howard Good ,  Kent E. Griffin ,  William Chambers Powell, III ,  George Easton Scott, III ,  Michael A. Toelle ,  John G. Torborg, Jr. ,  James E. Veres

IPC分类号： G06T11/00 ,  G06T13/80 ,  G06T15/00 ,  G06T15/04 ,  G06T15/60 ,  G06F15/00

CPC分类号： G06T13/80 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/60

摘要： A gsprite engine circuit reads a display list identifying gsprite image layers to be composited for display, retrieves gsprite image data from an external memory, and transforms the gsprite data to display device coordinates. The gsprite image layers represent independently rendered graphical objects in a graphics scene. The gsprite engine can simulate the motion of the graphical objects in a sequence of display images by performing affine transformations on the gsprite image layers. The interface to the gsprite engine circuit includes the display list and gsprite header blocks. The display list enumerates the gsprites to be composited as a display image. The header blocks describe a gsprite transform, which can be an affine transform, used to transform gsprites to display device coordinates. The header blocks also provide an array of references to image blocks or "chunks" comprising the gsprite.

摘要翻译： gsprite引擎电路读取识别将要合成显示的gsprite图像层的显示列表，从外部存储器检索gsprite图像数据，并将gsprite数据转换为显示设备坐标。 gsprite图像层表示图形场景中独立渲染的图形对象。 gsprite引擎可以通过在gsprite图像层上执行仿射变换来模拟图像对象在一系列显示图像中的运动。 gsprite引擎电路的接口包括显示列表和gsprite标题块。 显示列表列举要合成为显示图像的gsprites。 标题块描述了一个gsprite变换，它可以是仿射变换，用于将gsprites转换为显示设备坐标。 标题块还提供了包含gsprite的图像块或“块”的引用数组。

公开(公告)号：US5949428A

公开(公告)日：1999-09-07

申请号：US672694

申请日：1996-06-27

申请人： Michael A. Toelle ,  Mark L. Kenworthy

发明人： Michael A. Toelle ,  Mark L. Kenworthy

IPC分类号： G06T11/00 ,  G06T13/00 ,  G06T15/00 ,  G06T15/20 ,  G06T15/60 ,  G06F15/00

CPC分类号： G06T11/001 ,  G06T11/40 ,  G06T13/80 ,  G06T15/005 ,  G06T15/04 ,  G06T15/60

摘要： In a graphics rendering system, an apparatus for resolving depth sorted lists of pixel fragments includes color and alpha accumulators for computing color and alpha values from the pixel fragments in a fragment list. Pixel fragments include color, alpha, coverage data. The coverage data describes how a geometric primitive covers sub-pixel regions of a pixel using a coverage mask. Pixel circuitry according to a clock-optimized approach includes separate color and alpha accumulators for computing color and alpha values for sub-pixel regions of a pixel. The accumulated color values are then summed and scaled to compute final color values for a pixel. To reduce hardware requirements, pixel circuitry in a hardware-optimized approach recognizes that some pixel regions have common accumulated alpha values as each fragment layer is processed. As such, color contributions for fragment layers can be computed using a single color accumulation operation for a pixel region having common alpha values.

摘要翻译： 在图形渲染系统中，用于解析像素片段的深度排序列表的装置包括用于从片段列表中的像素片段计算颜色和α值的颜色和α累加器。 像素片段包括彩色，alpha，coverage数据。 覆盖数据描述几何图元如何使用覆盖掩码覆盖像素的子像素区域。 根据时钟优化方法的像素电路包括用于计算像素的子像素区域的颜色和α值的单独的颜色和α累加器。 然后将累加的颜色值相加和缩放以计算像素的最终颜色值。 为了降低硬件要求，硬件优化方法中的像素电路识别出，随着每个片段层被处理，某些像素区域具有共同的累积alpha值。 因此，可以使用对具有公共α值的像素区域的单个颜色累积操作来计算片段层的颜色贡献。

公开(公告)号：US09064334B2

公开(公告)日：2015-06-23

申请号：US13152452

申请日：2011-06-03

申请人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

发明人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

IPC分类号： G09G5/00 ,  G06T15/00 ,  G09G5/36 ,  G06T15/80 ,  G06T1/20 ,  G06T15/50

CPC分类号： G06T15/005 ,  G06T1/20 ,  G06T15/00 ,  G06T15/20 ,  G06T15/50 ,  G06T15/80 ,  G09G5/363

摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.

公开(公告)号：US08035646B2

公开(公告)日：2011-10-11

申请号：US10987120

申请日：2004-11-12

申请人： Charles N. Boyd ,  Michele B. Boland ,  Michael A. Toelle ,  Anantha Rao Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen H. Wright

发明人： Charles N. Boyd ,  Michele B. Boland ,  Michael A. Toelle ,  Anantha Rao Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen H. Wright

IPC分类号： G06T1/00

CPC分类号： G06F9/325 ,  G06F9/3842 ,  G06F9/3879 ,  G06T15/005 ,  G06T15/80

摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.

摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

公开(公告)号：US07978205B1

公开(公告)日：2011-07-12

申请号：US10933850

申请日：2004-09-03

申请人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

发明人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

IPC分类号： G09G5/00

CPC分类号： G06T15/005 ,  G06T1/20 ,  G06T15/00 ,  G06T15/20 ,  G06T15/50 ,  G06T15/80 ,  G09G5/363

摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.

摘要翻译： 提供了增强的图形流水线，其使公共核心硬件能够执行图形流水线的不同组件，由流水线中的组件包括线和三角形的原语的可编程性，以及在呈现与图形显示之间的流输出 数据在管道中。 编程人员不必优化代码，因为通用核心将平衡所需功能的负载，并在通用核心硬件上动态分配这些指令。 程序员可以使用算法编程原语，以通过用线和三角形进行拓扑替换来简化所有顶点计算。 程序员获取计算的输出数据，并在渲染之前或期间读取它们。 因此，程序员在编程中具有更大的灵活性。 通过使用增强型图形管线，程序员可以优化管道中硬件的使用，程序顶点，线或三角形拓扑，而不是单独使用每个顶点，并从管道可以输出计算的信息的内存读取任何计算的数据。