公开(公告)号：US08289261B2

公开(公告)日：2012-10-16

申请号：US12507316

申请日：2009-07-22

Applicant: Min-Cheol Lee ,  Yong-Soon Lee

Inventor： Min-Cheol Lee ,  Yong-Soon Lee

IPC: G09G3/36

CPC classification number: G09G3/3674 ,  G02F1/13454 ,  G09G3/3266 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2360/16 ,  G11C19/28

Abstract: A gate driving circuit that may be capable of improving driving margin and maintaining reliability even after long use, and a display device having the gate driving circuit. The gate driving circuit includes a shift register having a plurality of stages dependently connected to one another, wherein each stage includes a pull-up unit outputting a first clock signal as a gate signal in response to a signal of a first node, to which a first input signal is applied, a pull-down unit discharging the gate signal to a gate-off voltage in response to a second input signal, a discharging unit discharging the signal of the first node to the gate-off voltage in response to the second input signal, and a holding unit maintaining the signal of the first node at the gate-off voltage in response to a delay signal of the first clock signal.

Abstract translation: 一种能够在长时间使用后能够提高驱动余量并保持可靠性的栅极驱动电路，以及具有栅极驱动电路的显示装置。 栅极驱动电路包括具有相互依次连接的多个级的移位寄存器，其中每一级包括上拉单元，其响应于第一节点的信号而将第一时钟信号作为门信号输出， 施加第一输入信号，下拉单元响应于第二输入信号将门信号放电到栅极截止电压，放电单元响应于第二输入信号将第一节点的信号放电到栅极截止电压 输入信号和保持单元，其响应于第一时钟信号的延迟信号而将第一节点的信号保持在栅极截止电压。

公开(公告)号：US07834676B2

公开(公告)日：2010-11-16

申请号：US12357261

申请日：2009-01-21

Applicant: Woo-Geun Lee ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

Inventor： Woo-Geun Lee ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

IPC: G11C11/34

CPC classification number: G09G3/3648 ,  G09G2300/0413 ,  G09G2300/0819 ,  G09G2320/043

Abstract: A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage.

Abstract translation: 提出了一种用于考虑晶体管特性变化的装置。 该器件包括晶体管和比较器，其接收来自晶体管的反馈信号和参考信号。 比较器向偏置电压发生器提供输出。 偏置电压发生器包括连接到比较器的输出的输入端和连接到晶体管的输出。 在本发明的一些实施例中，晶体管是双栅极晶体管，并且偏置电压发生器被施加到双栅晶体管的顶栅，以便控制晶体管的特性，例如导通电压。

公开(公告)号：US20100182068A1

公开(公告)日：2010-07-22

申请号：US12357261

申请日：2009-01-21

Applicant: Woo-Geun LEE ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

Inventor： Woo-Geun LEE ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

IPC: G06G7/12

CPC classification number: G09G3/3648 ,  G09G2300/0413 ,  G09G2300/0819 ,  G09G2320/043

Abstract: A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage.

Abstract translation: 提出了一种用于考虑晶体管特性变化的装置。 该器件包括晶体管和比较器，其接收来自晶体管的反馈信号和参考信号。 比较器向偏置电压发生器提供输出。 偏置电压发生器包括连接到比较器的输出的输入端和连接到晶体管的输出。 在本发明的一些实施例中，晶体管是双栅极晶体管，并且偏置电压发生器被施加到双栅晶体管的顶栅，以便控制晶体管的特性，例如导通电压。

公开(公告)号：US20100039363A1

公开(公告)日：2010-02-18

申请号：US12507316

申请日：2009-07-22

Applicant: Min-Cheol LEE ,  Yong-Soon LEE

Inventor： Min-Cheol LEE ,  Yong-Soon LEE

IPC: G09G3/36

CPC classification number: G09G3/3674 ,  G02F1/13454 ,  G09G3/3266 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2360/16 ,  G11C19/28

Abstract: A gate driving circuit that may be capable of improving driving margin and maintaining reliability even after long use, and a display device having the gate driving circuit. The gate driving circuit includes a shift register having a plurality of stages dependently connected to one another, wherein each stage includes a pull-up unit outputting a first clock signal as a gate signal in response to a signal of a first node, to which a first input signal is applied, a pull-down unit discharging the gate signal to a gate-off voltage in response to a second input signal, a discharging unit discharging the signal of the first node to the gate-off voltage in response to the second input signal, and a holding unit maintaining the signal of the first node at the gate-off voltage in response to a delay signal of the first clock signal.

Abstract translation: 一种能够在长时间使用后能够提高驱动余量并保持可靠性的栅极驱动电路，以及具有栅极驱动电路的显示装置。 栅极驱动电路包括具有相互依次连接的多个级的移位寄存器，其中每一级包括上拉单元，其响应于第一节点的信号而将第一时钟信号作为门信号输出， 施加第一输入信号，下拉单元响应于第二输入信号将门信号放电到栅极截止电压，放电单元响应于第二输入信号将第一节点的信号放电到栅极截止电压 输入信号和保持单元，其响应于第一时钟信号的延迟信号而将第一节点的信号保持在栅极截止电压。

公开(公告)号：US07626649B2

公开(公告)日：2009-12-01

申请号：US11781112

申请日：2007-07-20

Applicant: Min-cheol Lee

Inventor： Min-cheol Lee

IPC: G02F1/136 ,  G02F1/133

CPC classification number: G02F1/1393 ,  G02F1/136213 ,  G09G3/3648 ,  G09G2320/0219 ,  G09G2320/0223

Abstract: A liquid crystal display device includes a first substrate which comprises a plurality of pixels where a thin film transistor and a pixel electrode electrically connected to the thin film transistor are formed, the first substrate including a gate line and a data line which insulatingly intersect each other; and a gate driver which applies a gate driving signal to the gate line, the thin film transistor including a gate electrode which is connected to the gate line; a source electrode which is connected to the data line; and a drain electrode which is connected to the pixel electrode, and the pixels being decreased in a value of Cp/(Cp+Clc+Cst) as going toward the gate driver (where, Cp: a sum of parasitic capacity between the gate electrode and the source electrode and parasitic capacity between the gate electrode and the drain electrode, Clc: liquid crystal capacity, and Cst: storage capacity).

Abstract translation: 液晶显示装置包括：第一基板，其包括形成薄膜晶体管和与薄膜晶体管电连接的像素电极的多个像素，第一基板包括栅极线和彼此绝缘地相交的数据线 ; 以及栅极驱动器，其对栅极线施加栅极驱动信号，所述薄膜晶体管包括连接到所述栅极线的栅电极; 连接到数据线的源电极; 以及连接到像素电极的漏电极，并且像素朝向栅极驱动器的Cp /（Cp + Clc + Cst）值减小（其中，Cp：栅电极之间的寄生电容之和 源电极和栅电极与漏电极之间的寄生电容，Clc：液晶容量，Cst：存储容量）。

公开(公告)号：US20090040161A1

公开(公告)日：2009-02-12

申请号：US12145140

申请日：2008-06-24

Applicant: Seung-Soo BAEK ,  Yong-Soon LEE ,  Min-Cheol LEE ,  Seong-Young LEE

Inventor： Seung-Soo BAEK ,  Yong-Soon LEE ,  Min-Cheol LEE ,  Seong-Young LEE

IPC: G09G3/36

CPC classification number: G09G3/3607 ,  G09G3/3614 ,  G09G3/3659 ,  G09G3/3677 ,  G09G2300/0814 ,  G09G2310/0205 ,  G09G2310/0251 ,  G09G2310/06 ,  G09G2320/0219 ,  G09G2320/0223 ,  G09G2320/0252 ,  G09G2320/0276 ,  G09G2320/028 ,  G11C19/28 ,  H03K5/15093

Abstract: A display apparatus includes a panel part having a plurality of gate lines, a plurality of data lines, a plurality of pixels, a data driver and a gate driver part. Each pixel of the plurality of pixels includes a first sub-pixel and a second sub-pixel. The first sub-pixel is connected to a first gate line of the plurality of gate lines and the second sub-pixel is connected to a second gate line of the plurality of gate lines. The first sub-pixel and the second sub-pixel are each commonly connected to one data line of the plurality of data lines. The gate driver part is disposed on the panel part and applies a plurality of gate signals to the plurality of gate lines. A current gate signal of the plurality of gate signals is temporally overlapped with a previous gate signal for a predetermined time interval.

Abstract translation: 显示装置包括具有多条栅极线，多条数据线，多个像素，数据驱动器和栅极驱动器部分的面板部分。 多个像素中的每个像素包括第一子像素和第二子像素。 第一子像素连接到多条栅极线的第一栅极线，第二子像素连接到多条栅极线的第二栅极线。 第一子像素和第二子像素都共同连接到多条数据线中的一条数据线。 栅极驱动器部分设置在面板部分上，并且对多个栅极线施加多个栅极信号。 多个门信号的当前门信号在预定的时间间隔内与先前的门信号暂时重叠。

公开(公告)号：US20080218502A1

公开(公告)日：2008-09-11

申请号：US11960131

申请日：2007-12-19

Applicant: Min-Cheol LEE ,  Byeong-Jae AHN ,  Jong-Hwan LEE ,  Yeon-Kyu MOON ,  Jong-Hyuk LEE

Inventor： Min-Cheol LEE ,  Byeong-Jae AHN ,  Jong-Hwan LEE ,  Yeon-Kyu MOON ,  Jong-Hyuk LEE

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G3/3674 ,  G09G2310/0286 ,  G11C19/182

Abstract: A display apparatus includes a gate driver which sequentially outputs a gate signal at a high state in response to a gate control signal and a data driver which converts image data into a data signal in response to a data control signal. The display apparatus further includes a display panel which includes a plurality of gate lines which sequentially receive the gate signal, a plurality of data lines which receive the data signal and a plurality of pixels connected to the gate and data lines and which receive the data signal in response to the gate signal to display an image. The polarity of the data signal is inverted after the gate signal transitions to a low state.

Abstract translation: 显示装置包括：栅极驱动器，其响应于栅极控制信号顺序地输出处于高状态的栅极信号;以及数据驱动器，其响应于数据控制信号将图像数据转换为数据信号。 显示装置还包括显示面板，其包括顺序地接收栅极信号的多个栅极线，接收数据信号的多个数据线和连接到栅极和数据线的多个像素，并且接收数据信号 响应于门信号显示图像。 在门信号转换到低电平状态之后，数据信号的极性反转。

公开(公告)号：US20080211760A1

公开(公告)日：2008-09-04

申请号：US11932532

申请日：2007-10-31

Applicant: Seung-Soo Baek ,  Yong Soon Lee ,  Min Cheol Lee ,  Young Bum Kim ,  Sang Jin Jeon

Inventor： Seung-Soo Baek ,  Yong Soon Lee ,  Min Cheol Lee ,  Young Bum Kim ,  Sang Jin Jeon

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G09G2320/0223 ,  G11C19/184

Abstract: A liquid crystal display and a dual gate driving circuit therefor wherein the number of signal lines are reduced by sharing a start pulse and an output signal of a dummy stage. The liquid crystal display includes a timing controller generating an output enable signal, a gate clock, and a signal start signal in response to an external input signal, a level shifter generating a gate clock pulse and a gate clock bar pulse in response to the output enable signal and the gate clock and generating a single start pulse in response to the start signal and the gate clock, and first and second gate driving circuits outputting the gate clock pulse or the gate clock bar pulse as a gate driving signal to the plurality of gate lines in response to the single start pulse.

Abstract translation: 一种液晶显示器及其双栅极驱动电路，其中通过共享虚拟级的起始脉冲和输出信号来减少信号线的数量。 液晶显示器包括响应于外部输入信号产生输出使能信号，门时钟和信号起始信号的定时控制器，响应于输出产生栅极时钟脉冲和栅极时钟脉冲脉冲的电平转换器 使能信号和栅极时钟，并且响应于起始信号和栅极时钟产生单个起始脉冲，并且第一和第二栅极驱动电路将栅极时钟脉冲或栅极时钟条脉冲作为栅极驱动信号输出到多个 响应于单个起始脉冲的栅极线。

公开(公告)号：US20080165110A1

公开(公告)日：2008-07-10

申请号：US11969597

申请日：2008-01-04

Applicant: Jeong Il Kim ,  Seung Soo Baek ,  Chang Soo Lee ,  Min Cheol Lee

Inventor： Jeong Il Kim ,  Seung Soo Baek ,  Chang Soo Lee ,  Min Cheol Lee

IPC: G09G3/36 ,  H01L21/336 ,  G05F1/10

CPC classification number: H01L27/124 ,  G02F1/136204 ,  G09G3/3677 ,  G09G2330/04 ,  G11C19/184 ,  G11C19/28 ,  H01L27/1214 ,  H01L27/1255

Abstract: A gate driving circuit including a plurality of stages dependently connected to one another. Each stage comprises a gate pad formed at one end of a gate line; a pull-up transistor outputting a gate driving signal for driving the gate line; a capacitor formed with a dielectric substance disposed between a first electrode connected to a gate electrode of the pull-up transistor and a second electrode connected to a drain electrode of the pull-up transistor; a first connecting electrode connecting the gate pad to the second electrode; a holding transistor connected to the pull-up transistor to maintain a voltage level of the gate driving signal; a switching transistor connected to the pull-up transistor and the capacitor to control the holding transistor through the gate driving signal; and a second connecting electrode connecting the second electrode to the gate electrode of the switching transistor.

Abstract translation: 一种栅极驱动电路，包括彼此依赖地连接的多个级。 每个级包括形成在栅极线的一端的栅极焊盘; 输出用于驱动栅极线的栅极驱动信号的上拉晶体管; 形成有电介质的电容器，设置在与上拉晶体管的栅电极连接的第一电极和连接到上拉晶体管的漏电极的第二电极之间; 将所述栅极焊盘连接到所述第二电极的第一连接电极; 连接到所述上拉晶体管以保持所述栅极驱动信号的电压电平的保持晶体管; 连接到上拉晶体管和电容器的开关晶体管，以通过栅极驱动信号控制保持晶体管; 以及将第二电极连接到开关晶体管的栅电极的第二连接电极。

公开(公告)号：US20080042950A1

公开(公告)日：2008-02-21

申请号：US11703414

申请日：2007-02-06

Applicant: Haeng-Won Park ,  Nam-Soo Kang ,  Yong-Soon Lee ,  Min-Cheol Lee

Inventor： Haeng-Won Park ,  Nam-Soo Kang ,  Yong-Soon Lee ,  Min-Cheol Lee

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/28

Abstract: A display substrate provides more reliable operation comprising a gate driver having groups of stages each connected to one end of each gate conductor of a respective group of gate conductors and groups of sub-gate drivers connected to the other end of the gate conductors of the respective groups of gate conductors, the gate drivers deliver driving signals to one end of the gate conductors of one group while the sub-gate drivers pull the other end of each of the gate conductors of the other group to a predetermined voltage.

Abstract translation: 显示基板提供更可靠的操作，其包括栅极驱动器，该栅极驱动器具有各自级的栅极驱动器，各级级分别连接到相应组栅极导体的每个栅极导体的一端和连接到相应的栅极导体的另一端的子栅极驱动器组 一组栅极导体，栅极驱动器将驱动信号传送到一组的栅极导体的一端，而子栅极驱动器将另一组的每个栅极导体的另一端拉到预定电压。