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    Thin film transistor display panel and manufacturing method of the same
    1.
    发明授权
    Thin film transistor display panel and manufacturing method of the same 有权
    薄膜晶体管显示面板及其制造方法相同

    公开(公告)号：US09184090B2

    公开(公告)日：2015-11-10

    申请号：US13151102

    申请日：2011-06-01

    Applicant: Seung-Ha Choi ,  Kyoung-Jae Chung ,  Woo-Geun Lee

    Inventor： Seung-Ha Choi ,  Kyoung-Jae Chung ,  Woo-Geun Lee

    IPC: H01L21/00 ,  H01L21/768 ,  G02F1/1333 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66

    CPC classification number: H01L21/76804 ,  G02F1/133345 ,  G02F1/136227 ,  G02F1/136286 ,  H01L21/76816 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

    Abstract: A TFT display panel having a high charge mobility and making it possible to obtain uniform electric characteristics with respect to a large-area display is provided as well as a manufacturing method thereof. A TFT display panel includes a gate electrode formed on an insulation substrate, a first gate insulting layer formed of SiNx on the gate electrode, a second gate insulting layer formed of SiOx on the first gate insulting layer, an oxide semiconductor layer formed to overlap the gate electrode and having a channel part, and a passivation layer formed of SiOx on the oxide semiconductor layer and the gate electrode, and the passivation layer includes a contact hole exposing the drain electrode. The contact hole has a shape in which the passivation layer of a portion directly exposed together with a metal occupies an area smaller than the upper passivation layer.

    Abstract translation: 提供具有高电荷迁移率并且可以获得相对于大面积显示器的均匀电特性的TFT显示面板及其制造方法。 TFT显示面板包括形成在绝缘基板上的栅极电极，栅极上由SiNx形成的第一栅极绝缘层，在第一栅极绝缘层上由SiOx形成的第二栅极绝缘层，形成为与栅极电极重叠的氧化物半导体层 栅电极，并具有通道部分，以及由氧化物半导体层和栅电极上的SiO x形成的钝化层，钝化层包括暴露漏电极的接触孔。 接触孔具有直接与金属一起暴露的部分的钝化层占据比上钝化层小的形状。

    Thin film transistor array substrate and method of fabricating the same
    2.
    发明授权
    Thin film transistor array substrate and method of fabricating the same 有权
    薄膜晶体管阵列基板及其制造方法

    公开(公告)号：US08994023B2

    公开(公告)日：2015-03-31

    申请号：US13115088

    申请日：2011-05-24

    Applicant: Hye-Young Ryu ,  Woo-Geun Lee ,  Young-Joo Choi ,  Kyoung-Jae Chung ,  Jin-Won Lee ,  Seung-Ha Choi ,  Hee-Jun Byeon ,  Pil-Sang Yun

    Inventor： Hye-Young Ryu ,  Woo-Geun Lee ,  Young-Joo Choi ,  Kyoung-Jae Chung ,  Jin-Won Lee ,  Seung-Ha Choi ,  Hee-Jun Byeon ,  Pil-Sang Yun

    IPC: H01L47/00 ,  H01L29/10 ,  H01L29/04 ,  H01L29/15 ,  H01L27/12

    CPC classification number: H01L27/1214 ,  H01L27/1225 ,  H01L27/1255

    Abstract: A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

    Abstract translation: 提供了能够降低由于氧化物半导体图案的劣化引起的器件劣化的薄膜晶体管阵列基板及其制造方法。 薄膜晶体管阵列基板可以包括其上形成有栅极的绝缘基板，形成在绝缘基板上的栅极绝缘膜，设置在栅极绝缘膜上的氧化物半导体图案，形成在氧化物半导体上的抗蚀刻图案 图案，以及形成在防蚀刻图案上的源电极和漏电极。 氧化物半导体图案可以包括位于源电极和漏电极之间的边缘部分，并且边缘部分可以包括至少一个导电区域和至少一个非导电区域。

    Thin-film transistor, method of fabricating the thin-film transistor, and display substrate using the thin-film transistor
    3.
    发明授权
    Thin-film transistor, method of fabricating the thin-film transistor, and display substrate using the thin-film transistor 有权
    薄膜晶体管，制造薄膜晶体管的方法以及使用该薄膜晶体管的显示基板

    公开(公告)号：US08476627B2

    公开(公告)日：2013-07-02

    申请号：US13046130

    申请日：2011-03-11

    Applicant: Pil-Sang Yun ,  Young-Wook Lee ,  Woo-Geun Lee

    Inventor： Pil-Sang Yun ,  Young-Wook Lee ,  Woo-Geun Lee

    IPC: H01L29/786

    CPC classification number: H01L21/467 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/7869

    Abstract: Provided is an oxide thin-film transistor (TFT) substrate that may enhance the display quality of a display device and a method of fabricating the same via a simple process. The oxide TFT substrate includes: a substrate, a gate line, a data line, an oxide TFT, and a pixel electrode. An oxide layer of the oxide TFT includes a first region that has semiconductor characteristics and a channel, and a second region that is conductive and surrounds the first region. A portion of the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line.

    Abstract translation: 提供了可以通过简单的处理来提高显示装置的显示质量的氧化物薄膜晶体管（TFT）基板及其制造方法。 氧化物TFT基板包括：基板，栅极线，数据线，氧化物TFT和像素电极。 氧化物TFT的氧化物层包括具有半导体特性的第一区域和沟道，以及导电并围绕第一区域的第二区域。 第一区域的一部分电连接到像素电极，并且第二区域电连接到数据线。

    Vertical channel thin-film transistor and method of manufacturing the same
    6.
    发明授权
    Vertical channel thin-film transistor and method of manufacturing the same 有权
    垂直通道薄膜晶体管及其制造方法

    公开(公告)号：US08203662B2

    公开(公告)日：2012-06-19

    申请号：US12571345

    申请日：2009-09-30

    Applicant: Hoon Kang ,  Yun-Seok Lee ,  Jae-Sung Kim ,  Yang-Ho Jung ,  Young-Je Cho ,  Cheon-Jae Maeng ,  Woo-Geun Lee

    Inventor： Hoon Kang ,  Yun-Seok Lee ,  Jae-Sung Kim ,  Yang-Ho Jung ,  Young-Je Cho ,  Cheon-Jae Maeng ,  Woo-Geun Lee

    IPC: G02F1/136 ,  H01L29/04 ,  H01L29/10 ,  H01L31/00 ,  H01L27/14 ,  H01L29/15 ,  H01L31/036

    CPC classification number: H01L29/78642 ,  H01L27/12 ,  H01L29/42384

    Abstract: Provided is a thin-film transistor (TFT) substrate. The TFT substrate includes: an insulating substrate; a semiconductor pattern which is formed on the insulating substrate, the semiconductor pattern having a top surface and a bottom surface; a source electrode and a drain electrode which are disposed on the top and bottom surfaces of the semiconductor pattern, respectively; a gate electrode which is disposed alongside the semiconductor pattern with a gate insulating film interposed therebetween; a data line which is connected to the source electrode and extends in a first direction; a gate line which is connected to the gate electrode and extends in a second direction; and a pixel electrode which is connected to the drain electrode and is formed in a pixel region.

    Abstract translation: 提供了薄膜晶体管（TFT）基板。 TFT基板包括：绝缘基板; 形成在所述绝缘基板上的半导体图案，所述半导体图案具有顶面和底面; 源电极和漏电极，分别设置在半导体图案的顶表面和底表面上; 栅极电极，其间设置有栅极绝缘膜并且位于半导体图案的旁边; 数据线，其连接到所述源电极并沿第一方向延伸; 栅极线，其连接到所述栅电极并沿第二方向延伸; 以及连接到漏电极并形成在像素区域中的像素电极。

    DISPLAY SUBSTRATE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE
    7.
    发明申请
    DISPLAY SUBSTRATE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE 有权
    显示基板，显示装置以及制造显示基板的方法

    公开(公告)号：US20120113346A1

    公开(公告)日：2012-05-10

    申请号：US13277114

    申请日：2011-10-19

    Applicant: Seung-Ha CHOI ,  Kyoung-Jae Chung ,  Woo-Geun Lee

    Inventor： Seung-Ha CHOI ,  Kyoung-Jae Chung ,  Woo-Geun Lee

    IPC: G02F1/136 ,  H01L33/08

    CPC classification number: H01L21/3086 ,  G02F1/136227 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

    Abstract: Provided are a display substrate, a display device, and a method of manufacturing the display substrate. The display substrate includes: a substrate in which a pixel region is defined; a gate electrode and a gate pad are formed on the substrate; a gate insulating layer formed on the gate electrode and the gate pad; a buffer layer pattern overlaps the gate electrode and is formed on the gate insulating layer; an insulating film pattern formed on the buffer layer pattern; an oxide semiconductor pattern formed on the insulating film pattern; a source electrode formed on the oxide semiconductor pattern; and a drain electrode formed on the oxide semiconductor pattern and is separated from the source electrode.

    Abstract translation: 提供了显示基板，显示装置和制造显示基板的方法。 显示基板包括：限定像素区域的基板; 在基板上形成栅电极和栅极焊盘; 形成在栅极电极和栅极焊盘上的栅极绝缘层; 缓冲层图案与栅电极重叠并形成在栅极绝缘层上; 形成在缓冲层图案上的绝缘膜图案; 形成在所述绝缘膜图案上的氧化物半导体图案; 形成在所述氧化物半导体图案上的源电极; 以及形成在氧化物半导体图案上并与源电极分离的漏电极。

    Thin film transistor array panel and fabrication
    8.
    发明授权
    Thin film transistor array panel and fabrication 有权
    薄膜晶体管阵列和制造

    公开(公告)号：US08173493B2

    公开(公告)日：2012-05-08

    申请号：US12765698

    申请日：2010-04-22

    Applicant: Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

    Inventor： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

    IPC: H01L21/00 ,  H01L21/84

    CPC classification number: H01L27/124 ,  G02F2001/13629 ,  H01L29/458

    Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

    Abstract translation: 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

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