公开(公告)号：US06009513A

公开(公告)日：1999-12-28

申请号：US261116

申请日：1999-03-03

申请人： Rupaka Mahalingaiah ,  Paul K. Miller

发明人： Rupaka Mahalingaiah ,  Paul K. Miller

IPC分类号： G06F9/28 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/28 ,  G06F9/30152 ,  G06F9/3816 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A superscalar microprocessor implements a microcode instruction unit with sequence control fields appended to each microcode line. The sequence control fields indicate whether a subsequent line contains a branch instruction, whether a subsequent line is the last line in a microcode sequence, and other sequence control information. The sequence control information is accessed one cycle before the microcode line. This allows the next address to be calculated in parallel with the accessing of the microcode instruction line. By generating the next address in parallel with accessing the microcode line, the time delay from accessing one microcode line to accessing the next microcode line is reduced. The sequence control field additionally indicates how many microcode instructions are in the last line of the microcode sequence. If the last microcode line of the microcode sequence contains less instructions than the number of issue positions available, fastpath, or directly decodable instructions, can be issued with the final microcode line.

公开(公告)号：US5913047A

公开(公告)日：1999-06-15

申请号：US960189

申请日：1997-10-29

申请人： Rupaka Mahalingaiah ,  Paul K. Miller

发明人： Rupaka Mahalingaiah ,  Paul K. Miller

IPC分类号： G06F9/30 ,  G06F9/315 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/382 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3853 ,  G06F9/3857

摘要： A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction. The predecode unit marks the two instructions as a single instruction. A start bit is asserted for the first byte of the floating point exchange instruction and an end bit is asserted for the last byte of the floating point instruction. The combined instruction is dispatched into the instruction execution pipeline. A decode unit decodes the opcodes of the two instructions and passes the opcode of the floating point instruction to the floating point unit and passes exchange register information to the floating point unit. The exchange register information includes a sufficient number of bits to specify a floating point register and a valid bit. The floating point instruction unit receives the exchange register information, exchanges the top-of-stack with the register specified by the exchange register information and then performs the floating point operation. In the above manner, two floating point operations may be executed in a single clock cycle.

摘要翻译： 微处理器检测浮点交换指令后跟浮点指令，并将两条指令作为一个组合指令分派到浮点单元。 预解码单元将两个指令标记为单个指令。 对于浮点交换指令的第一个字节，一个起始位被置位，而对于浮点指令的最后一个字节，一个结束位被置位。 组合指令被分派到指令执行管道中。 解码单元解码两个指令的操作码，并将浮点指令的操作码传递到浮点单元，并将交换寄存器信息传递给浮点单元。 交换寄存器信息包括足够数量的位以指定浮点寄存器和有效位。 浮点指令单元接收交换寄存器信息，与由交换寄存器信息指定的寄存器交换栈顶，然后执行浮点运算。 以上述方式，可以在单个时钟周期中执行两个浮点运算。

公开(公告)号：US5548544A

公开(公告)日：1996-08-20

申请号：US323484

申请日：1994-10-14

申请人： David T. Matheny ,  Paul K. Miller ,  Michael P. Taborn

发明人： David T. Matheny ,  Paul K. Miller ,  Michael P. Taborn

IPC分类号： G06F7/38 ,  G06F7/483 ,  G06F7/57 ,  G06F17/10

CPC分类号： G06F7/483 ,  G06F7/49957

摘要： An apparatus for rounding an answer produced during the execution of an operation by a multiple stage execution pipeline includes first circuitry for detecting when the operation is iterative and accuracy bits associated with the answer to determine if a rounding calculation is required. When the first circuitry detects a rounding calculation is required, it sets a correction factor for the answer in accordance with a rounding mode and the detected accuracy. In a method practiced by the apparatus, the rounding an answer produced during the execution of an operation occurs through the steps of detecting, when the operation is iterative, accuracy bits associated with the answer to determine if a rounding calculation is required, and, when the rounding calculation is required, setting a correction factor for the answer in accordance with a rounding mode and the detected accuracy bits.

摘要翻译： 用于舍入在多级执行流水线执行操作期间产生的应答的装置包括用于检测何时该操作是迭代的第一电路以及与该应答相关联的精确位以确定是否需要舍入计算。 当第一电路检测到需要舍入计算时，它根据舍入模式和检测到的精度设置答案的校正因子。 在该装置实施的方法中，在执行操作期间产生的回答的舍入是通过以下步骤发生的：当操作是迭代时，检测与答案相关联的精度位，以确定是否需要舍入计算，以及何时 需要舍入计算，根据舍入模式和检测到的精度位设置答案的校正因子。