公开(公告)号：US20100127682A1

公开(公告)日：2010-05-27

申请号：US12622500

申请日：2009-11-20

申请人： Stewart Kenly ,  Paul W. Latham, II

发明人： Stewart Kenly ,  Paul W. Latham, II

IPC分类号： G05F1/10

CPC分类号： H02M3/1588 ,  H02M3/157 ,  Y02B70/1466

摘要： In one embodiment, the method of these teachings includes decomposing the output ripple voltage into its constituent components and utilizing the scale factor necessary for this decomposition to obtain the measure capacitance and ESR for a power supply/converter.

摘要翻译： 在一个实施例中，这些教导的方法包括将输出纹波电压分解成其组成部件并利用该分解所需的比例因子来获得电源/转换器的测量电容和ESR。

公开(公告)号：US5331218A

公开(公告)日：1994-07-19

申请号：US912382

申请日：1992-07-13

申请人： Kristaan L. Moody ,  Paul W. Latham, II

发明人： Kristaan L. Moody ,  Paul W. Latham, II

IPC分类号： H03H11/12 ,  H03H19/00 ,  H03K5/00

CPC分类号： H03H19/004

摘要： A notch filter circuit includes first and second operational amplifiers, each having a capacitor connected from the amplifier output to the input. A third capacitor is connected between the second-amplifier input and the filter circuit input. A first switched-capacitor resistor is connected between the filter circuit input and the first-amplifier input. A second switched-capacitor resistor is connected between the first amplifier output and the second amplifier input. The second-amplifier output is connected to the filter circuit output. A third switched-capacitor resistor is connected between said filter circuit output and said first amplifier input; First and second programmable capacitor arrays are connected respectively in parallel with the third switched-capacitor resistor and in parallel with the first switched-capacitor resistor, so that a change only in the capacitance of the second capacitor array causes a corresponding change in the filter notch depth and a change only in the capacitance of the first capacitor array causes a corresponding change in the filter notch width. The first and second capacitor arrays each have a group of digital programming terminals that may be connected together for making fixed the ratio of the capacitance values of the two arrays. A digitally programmable voltage divider circuit connected in series with the second programmable capacitor array permits the independent programing of notch depth, i.e. without affecting notch width.

摘要翻译： 陷波滤波电路包括第一和第二运算放大器，每个具有从放大器输出端连接到输入端的电容器。 第二电容器连接在第二放大器输入端和滤波电路输入端之间。 第一个开关电容电阻连接在滤波电路输入端和第一放大器输入端之间。 第二开关电容电阻连接在第一放大器输出端和第二放大器输入端之间。 第二放大器输出连接到滤波电路输出。 第三开关电容电阻连接在所述滤波电路输出端与所述第一放大器输入端之间; 第一和第二可编程电容器阵列分别与第三开关电容器电阻并联连接，并且与第一开关电容器电阻并联，使得仅在第二电容器阵列的电容中的变化导致滤波器陷波的相应变化 深度和仅第一电容器阵列的电容的变化导致滤波器陷波宽度的相应变化。 第一和第二电容器阵列各自具有可以连接在一起的一组数字编程端子，用于固定两个阵列的电容值的比率。 与第二可编程电容器阵列串联连接的数字可编程分压器电路允许对凹口深度进行独立编程，即不影响切口宽度。

公开(公告)号：US5212456A

公开(公告)日：1993-05-18

申请号：US753483

申请日：1991-09-03

申请人： Thomas J. Kovalcik ,  Paul W. Latham, II

发明人： Thomas J. Kovalcik ,  Paul W. Latham, II

IPC分类号： H03F1/02 ,  H03F3/45 ,  H03F3/50

CPC分类号： H03F1/0261 ,  H03F3/45076 ,  H03F3/505

摘要： An amplifier has a first stage employing a pair of differentially connected NMOS amplifier transistors, a second stage composed of a bipolar current mirror circuit and two charge pumps. Each charge pump may be a switching voltage multiplier circuit without the conventional output capacitor. The outputs of the two charge pumps are connected, respectively, to the collector of the current-mirror output transistor and to the commonly connected sources of the NMOS amplifier transistors. Each charge pump serves as both a pulse-voltage energizing source and a load to the amplifier. The amplifier is incorporated with a high-current NMOS transistor in an integrated circuit, wherein one differential input of the amplifier is connected to the source of the driver transistor at which an external load, e.g. a motor, may be connected. The output (collector) of the differential amplifier is connected to the gate of the NMOS driver transistor so that the load current through the driver transistor is held regulated to a value proportional to the input or reference voltage that is applied to the other input of the differential amplifier. The peak pulse voltage of each charge pump is greater than the DC supply voltage from which the driver transistor and the two charge pumps are energized so that the dynamic range of both the input control voltage and the amplifier output to the gate of the NMOS driver transistor is much greater than the DC supply voltage to the integrated circuit.

摘要翻译： 放大器具有采用一对差分连接的NMOS放大器晶体管的第一级，由双极电流镜电路和两个电荷泵组成的第二级。 每个电荷泵可以是没有常规输出电容器的开关电压倍增器电路。 两个电荷泵的输出分别连接到电流镜输出晶体管的集电极和NMOS放大器晶体管的共同连接的源极。 每个电荷泵充当脉冲电压激励源和放大器的负载。 放大器与集成电路中的高电流NMOS晶体管结合，其中放大器的一个差分输入端连接到驱动晶体管的源极，在该源极处外部负载，例如， 可以连接电机。 差分放大器的输出（集电极）连接到NMOS驱动晶体管的栅极，使得通过驱动晶体管的负载电流被保持在与输入或参考电压成正比的值上， 差分放大器。 每个电荷泵的峰值脉冲电压大于驱动晶体管和两个电荷泵通电的直流电源电压，使得输入控制电压和放大器输出到NMOS驱动晶体管的栅极的动态范围 比集成电路的直流电源电压大得多。

公开(公告)号：US4695747A

公开(公告)日：1987-09-22

申请号：US749155

申请日：1985-06-26

申请人： Paul W. Latham, II

发明人： Paul W. Latham, II

IPC分类号： H03K17/74 ,  H03L7/089

CPC分类号： H03L7/0896

摘要： An improved current pump for use in a Type II phase-locked loop including diodes employed as on-off switches for completing paths for a source current. Apparatus is disclosed for increasing the switching speeds of the diodes by ensuring that diode bias voltages undergo the smallest possible shifts required to switch the diodes.

摘要翻译： 一种改进的电流泵，用于II型锁相环，包括用作完成源电流路径的开 - 关开关的二极管。 公开了用于通过确保二极管偏置电压经历切换二极管所需的最小可能偏移来增加二极管的开关速度的装置。

公开(公告)号：US4636748A

公开(公告)日：1987-01-13

申请号：US749156

申请日：1985-06-26

申请人： Paul W. Latham, II

发明人： Paul W. Latham, II

IPC分类号： H03L7/089 ,  H03L7/00

CPC分类号： H03L7/0896

摘要： An improved charge pump for use in a phase-locked loop is disclosed in which there is only one current source, and in which all switching components pass current in the same direction. The charge pump may thus be constructed entirely of NPN transistors, which makes it possible to embody it in a single integrated circuit chip. The pump up and pump down currents inherently have the same magnitude and transient characteristics, thus minimizing steady-state errors.

摘要翻译： 公开了一种用于锁相环的改进的电荷泵，其中仅有一个电流源，并且其中所有开关元件在同一方向上通过电流。 因此，电荷泵可以完全由NPN晶体管构成，这使得可以将其体现在单个集成电路芯片中。 泵浦和抽吸电流固有地具有相同的幅度和瞬态特性，从而最小化稳态误差。

公开(公告)号：US08629663B2

公开(公告)日：2014-01-14

申请号：US13078283

申请日：2011-04-01

申请人： Paul W. Latham, II ,  Mansur B. Kiadeh ,  Sudha Durvasula

发明人： Paul W. Latham, II ,  Mansur B. Kiadeh ,  Sudha Durvasula

IPC分类号： G05F1/577

CPC分类号： H02M3/158 ,  H02M3/07 ,  H02M2001/0006 ,  H02M2001/009

摘要： A first control system for a power supply includes a switch-mode DC-DC converter module and an FET gate drive module. The switch-mode DC-DC converter module receives an input voltage and generates first and second voltages, the first voltage powering a DC-DC control module. The FET gate drive module selectively drives a plurality of FETs of the power supply using the second voltage thereby generating a desired output voltage from the input voltage. A second control system is directed to driving the second voltage to a desired gate voltage, wherein the desire gate voltage is determined based on at least one of a plurality of operating parameters. A third control system includes controlling first and second voltages generated by a SIDO voltage converter based on the first and second voltages and a damping factor, and generating the damping factor based on current flowing through the inductor of the SIDO voltage converter.

摘要翻译： 用于电源的第一控制系统包括开关模式DC-DC转换器模块和FET栅极驱动模块。 开关模式DC-DC转换器模块接收输入电压并产生第一和第二电压，第一电压为DC-DC控制模块供电。 FET栅极驱动模块使用第二电压选择性地驱动电源的多个FET，从而从输入电压产生期望的输出电压。 第二控制系统旨在将第二电压驱动到期望的栅极电压，其中期望栅极电压基于多个操作参数中的至少一个来确定。 第三控制系统包括基于第一和第二电压和阻尼因子来控制由SIDO电压转换器产生的第一和第二电压，并且基于流过SIDO电压转换器的电感器的电流产生阻尼因子。

公开(公告)号：US08384363B2

公开(公告)日：2013-02-26

申请号：US12761718

申请日：2010-04-16

申请人： Paul W. Latham, II ,  Stewart Kenly

发明人： Paul W. Latham, II ,  Stewart Kenly

IPC分类号： G05F1/613

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： A method and apparatus for converting a DC voltage to a lower DC voltage, provides for conducting current from an input terminal, through an inductor to charge a capacitor connected to the inductor at an output terminal and to provide a varying range of load current from the output terminal, alternately switching the input terminal between a supply voltage and a ground potential to produce a desired voltage at the output terminal that is lower than the supply voltage, while providing the varying range of load current, and disconnecting the input terminal from both the supply voltage and the ground potential to reduce an increase in voltage at the output terminal caused by a substantial reduction in the load current, while current through the inductor adjusts in response to the reduced load current.

公开(公告)号：US20120249103A1

公开(公告)日：2012-10-04

申请号：US13078283

申请日：2011-04-01

申请人： Paul W. Latham, II ,  Mansur B. Kiadeh ,  Sudha Durvasula

发明人： Paul W. Latham, II ,  Mansur B. Kiadeh ,  Sudha Durvasula

IPC分类号： G05F1/46

CPC分类号： H02M3/158 ,  H02M3/07 ,  H02M2001/0006 ,  H02M2001/009

摘要： A first control system for a power supply includes a switch-mode DC-DC converter module and an FET gate drive module. The switch-mode DC-DC converter module receives an input voltage and generates first and second voltages, the first voltage powering a DC-DC control module. The FET gate drive module selectively drives a plurality of FETs of the power supply using the second voltage thereby generating a desired output voltage from the input voltage. A second control system is directed to driving the second voltage to a desired gate voltage, wherein the desire gate voltage is determined based on at least one of a plurality of operating parameters. A third control system includes controlling first and second voltages generated by a SIDO voltage converter based on the first and second voltages and a damping factor, and generating the damping factor based on current flowing through the inductor of the SIDO voltage converter.

摘要翻译： 用于电源的第一控制系统包括开关模式DC-DC转换器模块和FET栅极驱动模块。 开关模式DC-DC转换器模块接收输入电压并产生第一和第二电压，第一电压为DC-DC控制模块供电。 FET栅极驱动模块使用第二电压选择性地驱动电源的多个FET，从而从输入电压产生期望的输出电压。 第二控制系统旨在将第二电压驱动到期望的栅极电压，其中期望栅极电压基于多个操作参数中的至少一个来确定。 第三控制系统包括基于第一和第二电压和阻尼因子来控制由SIDO电压转换器产生的第一和第二电压，并且基于流过SIDO电压转换器的电感器的电流产生阻尼因子。

公开(公告)号：US08164320B2

公开(公告)日：2012-04-24

申请号：US13012453

申请日：2011-01-24

申请人： Paul W. Latham, II ,  Stewart Kenly ,  Laszlo Balogh

发明人： Paul W. Latham, II ,  Stewart Kenly ,  Laszlo Balogh

IPC分类号： G05F1/00

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： A system includes a first switch connected to a voltage input and a switching node. A second switch is connected to the switching node and a reference potential. A first circuit generates first rising edges and first falling edges by comparing a voltage at the switching node to a first voltage reference. The first voltage reference is between the reference potential and the voltage input. A second circuit generates second rising edges and second falling edges by comparing the switching node voltage to a second voltage reference. The second voltage reference is less than the reference potential. The controller calculates delay times based on the first rising edges, the first falling edges, the second rising edges and the second falling edges. The controller generates drive signals for the first switch and the second switch based on a duty cycle and the delay times.

摘要翻译： 系统包括连接到电压输入和开关节点的第一开关。 第二开关连接到开关节点和参考电位。 第一电路通过将开关节点处的电压与第一参考电压进行比较来产生第一上升沿和第一下降沿。 第一个参考电压在参考电位和电压输入之间。 第二电路通过将开关节点电压与第二参考电压进行比较来产生第二上升沿和第二下降沿。 第二个参考电压小于参考电位。 控制器基于第一上升沿，第一下降沿，第二上升沿和第二下降沿计算延迟时间。 控制器基于占空比和延迟时间产生第一开关和第二开关的驱动信号。

公开(公告)号：US20120062290A1

公开(公告)日：2012-03-15

申请号：US13301175

申请日：2011-11-21

申请人： Stewart Kenly ,  Paul W. Latham, II

发明人： Stewart Kenly ,  Paul W. Latham, II

IPC分类号： H03L7/08 ,  H03K7/08

CPC分类号： H03K7/08

摘要： In one embodiment, the digital pulse width modulator of these teachings includes comparators and a number of phases and capable of increasing resolution without increasing clock frequency. In another embodiment, the digital pulse width modulator (DPWM) of these teachings includes equality comparators and a number of phases and increases resolution without increasing clock frequency. A further embodiment of the system of these teachings includes a priority encoded comparator component (in one instance including a number of comparators) comparing duty cycle commands against preset minimums, that embodiment being referred to as a frequency Foldback component. Other embodiments and embodiments of the method of these teachings are also disclosed.

摘要翻译： 在一个实施例中，这些教导的数字脉冲宽度调制器包括比较器和多个相位，并且能够在不增加时钟频率的情况下提高分辨率。 在另一个实施例中，这些教导的数字脉冲宽度调制器（DPWM）包括相等比较器和多个相位，并且在不增加时钟频率的情况下增加分辨率。 这些教导的系统的另一实施例包括将占空比命令与预设最小值进行比较的优先编码比较器部件（在一个实例中包括多个比较器），该实施例被称为频率折返部件。 还公开了这些教导的方法的其他实施例和实施例。