公开(公告)号：US4020471A

公开(公告)日：1977-04-26

申请号：US591905

申请日：1975-06-30

申请人： William E. Woods ,  Philip E. Stanley

发明人： William E. Woods ,  Philip E. Stanley

IPC分类号： G06F13/26 ,  G06F9/18

CPC分类号： G06F13/26

摘要： In a data processing system, interrupt service is provided for any one of a plurality of interrupt sources which presents an interrupt signal which has a higher interrupt level than that of the currently active source. Interrupt flags are provided for each potential interrupt source, which flags are activated in response to the receipt of an interrupt signal from the interrupt source associated therewith. A scan for the highest interrupt level is made and interrupt service is provided for the interrupt source associated therewith.

摘要翻译： 在数据处理系统中，为多个中断源中的任何一个提供中断服务，该中断源提供具有比当前活动源更高的中断级别的中断信号。 为每个潜在的中断源提供中断标志，响应于从中断源接收到的中断信号，这些标志被激活。 对最高中断级进行扫描，并为与其相关联的中断源提供中断服务。

公开(公告)号：US3984820A

公开(公告)日：1976-10-05

申请号：US591966

申请日：1975-06-30

申请人： Philip E. Stanley ,  William E. Woods

发明人： Philip E. Stanley ,  William E. Woods

IPC分类号： G06F9/48 ,  G06F9/06

CPC分类号： G06F9/4831

摘要： A data processing system having a plurality of interrupt sources coupled to provide interrupt handling of a process currently executing at a specified interrupt level. A level change signal which may be generated by the process itself may change the specified level of such process to another level which may make such process less interruptable to other interrupt sources. The level change provided takes place without interrupting the execution of such process.

摘要翻译： 一种具有多个中断源的数据处理系统，其耦合以提供当前在指定中断级别执行的进程的中断处理。 可以由过程本身产生的电平变化信号可以将这种处理的指定级别改变到另一个级别，这可以使得这种处理对其他中断源的中断更少。 提供的级别更改在不中断执行此过程的情况下进行。

公开(公告)号：US4467417A

公开(公告)日：1984-08-21

申请号：US302903

申请日：1981-09-16

申请人： William E. Woods ,  David E. Cushing ,  Richard A. Lemay ,  Philip E. Stanley

发明人： William E. Woods ,  David E. Cushing ,  Richard A. Lemay ,  Philip E. Stanley

IPC分类号： G06F9/318 ,  G06F13/00

CPC分类号： G06F9/30181 ,  G06F9/3016 ,  G06F9/325

摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。

公开(公告)号：US4349874A

公开(公告)日：1982-09-14

申请号：US140630

申请日：1980-04-15

申请人： William E. Woods ,  Philip E. Stanley ,  David E. Cushing ,  Richard A. Lemay

发明人： William E. Woods ,  Philip E. Stanley ,  David E. Cushing ,  Richard A. Lemay

IPC分类号： G06F12/08 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F2212/6022

摘要： In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit. The requested procedural data words and non-procedural data words are transferred to the central processing unit by an interfacing device including a data bus latch for receiving the procedural data words and non-procedural data words transferred from the memory, a prefetch buffer for storing up to four words, a first set of OR gate circuits for selectively transferring the procedural data words stored in the prefetch buffer to a procedural data multiplexer for assembling either a procedural data word or a procedure address, and a second set of OR gate circuits for selectively transferring either a procedural data word or non-procedural data word to the source bus or a procedural data address or non-procedural data address to the source bus for transfer to the central processor unit.

摘要翻译： 在数据处理系统中，中央处理器单元请求存储在系统存储器中的过程数据字或非程序数据字。 控制存储设备执行固件指令，其包括本地总线字段，用于控制所请求的过程数据字和非程序数据字向中央处理器单元的传送。 所请求的程序数据字和非程序数据字通过包括用于接收程序数据字的数据总线锁存器和从存储器传送的非程序数据字的接口装置传送到中央处理器，用于存储的预取缓冲器 四个字，第一组OR门电路，用于选择性地将存储在预取缓冲器中的程序数据字传送到程序数据多路复用器，用于组装程序数据字或程序地址，以及第二组OR门电路，用于选择性地 将程序数据字或非程序数据字传送到源总线或程序数据地址或非程序数据地址到源总线以传送到中央处理器单元。

公开(公告)号：US4241418A

公开(公告)日：1980-12-23

申请号：US854301

申请日：1977-11-23

申请人： Philip E. Stanley

发明人： Philip E. Stanley

IPC分类号： G06F1/08 ,  H03K3/78 ,  H03K5/04 ,  H03K5/159

CPC分类号： H03K3/78 ,  G06F1/08

摘要： A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a delay line coupled to an INVERTER. By using a second delay line to delay the rectangular wave by a selectable predetermined delay period, a control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to that of the rectangular wave clock cycle period plus the period of the second predetermined delay. The addition of a synchronization circuit permits the clock cycle period to be dynamically selected during a clock cycle. This provides a rectangular train with the period of each clock cycle being any of the predetermined clock cycle periods independent of the clock cycle period of preceding or succeeding clock cycles.

摘要翻译： 一种用于提供矩形波形或波列的时钟系统，每个波段具有可选择的预定时钟周期周期。 由发生器产生矩形波列，该发生器包括耦合到逆变器的延迟线。 通过使用第二延迟线将矩形波延迟可选择的预定延迟周期，形成控制信号，当控制信号被馈送到发生器中时，产生具有等于矩形波时钟周期周期的时钟周期周期的第二矩形波列 加上第二预定延迟的周期。 添加同步电路允许在时钟周期期间动态地选择时钟周期周期。 这提供了一个矩形列，其中每个时钟周期的周期是与前一个或后续时钟周期的时钟周期周期无关的任何预定时钟周期。

公开(公告)号：US4047247A

公开(公告)日：1977-09-06

申请号：US674517

申请日：1976-04-07

申请人： Philip E. Stanley ,  William E. Woods ,  Kenneth J. Izbicki

发明人： Philip E. Stanley ,  William E. Woods ,  Kenneth J. Izbicki

IPC分类号： G06F9/355 ,  G06F9/20

CPC分类号： G06F9/355

摘要： A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an index address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. The addressed control store word provides signals for controlling the operation of the system, including the branching between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.

摘要翻译： 操作数的最终有效地址在微程序数据处理系统中通过使用可包括无索引地址的基址寄存器，可包括索引地址值的索引寄存器，可包括指令字的指令寄存器， 该指令字取决于多个测试条件中所选择的一个的状态来提供对控制存储器的寻址的控制。 寻址的控制存储字提供用于控制系统操作的信号，包括在诸如指令获取，寻址，读取，写入和执行之类的主要操作之间的分支以及在主要操作中包括的次要操作之间的分支。