Data processing system, method and interconnect fabric supporting a node-only broadcast
    21.
    发明授权
    Data processing system, method and interconnect fabric supporting a node-only broadcast 失效
    支持节点广播的数据处理系统,方法和互连结构

    公开(公告)号:US07483428B2

    公开(公告)日:2009-01-27

    申请号:US11054934

    申请日:2005-02-10

    IPC分类号: H04L12/28

    摘要: A data processing system includes a first processing node and a second processing node coupled by an interconnect fabric. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. The first processing units in the first processing node have a first mode in which the first processing units broadcast operations with a first scope limited to the first processing node and a second mode in which the first processing units of the first processing node broadcast operations with a second scope including the first processing node and the second processing node.

    摘要翻译: 数据处理系统包括由互连结构耦合的第一处理节点和第二处理节点。 第一处理节点包括彼此耦合以进行通信的多个第一处理单元,并且第二处理节点包括彼此耦合以进行通信的多个第二处理单元。 第一处理节点中的第一处理单元具有第一模式,其中第一处理单元以第一范围广播操作限于第一处理节点和第二模式,其中第一处理节点的第一处理单元以 第二范围包括第一处理节点和第二处理节点。

    Data processing system, method and interconnect fabric supporting concurrent operations of varying broadcast scope
    22.
    发明授权
    Data processing system, method and interconnect fabric supporting concurrent operations of varying broadcast scope 失效
    数据处理系统,方法和互连结构支持不同广播范围的并发操作

    公开(公告)号:US07474658B2

    公开(公告)日:2009-01-06

    申请号:US11054820

    申请日:2005-02-10

    IPC分类号: H04L12/28

    摘要: A data processing system includes a first processing node and a second processing node coupled by an interconnect fabric. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. A first processing unit in the first processing node includes interconnect logic that processes a plurality of concurrently pending broadcast operations of differing broadcast scope. At least a first of the plurality of concurrently pending broadcast operations has a first scope limited to the first processing node, and at least a second of the plurality of concurrently pending broadcast operations has a second scope including the first processing node and the second processing node.

    摘要翻译: 数据处理系统包括由互连结构耦合的第一处理节点和第二处理节点。 第一处理节点包括彼此耦合以进行通信的多个第一处理单元,并且第二处理节点包括彼此耦合以进行通信的多个第二处理单元。 第一处理节点中的第一处理单元包括处理不同广播范围的多个同时待决广播操作的互连逻辑。 多个同时待处理的广播操作中的至少第一个具有限于第一处理节点的第一范围,并且多个同时待处理的广播操作中的至少一个具有包括第一处理节点和第二处理节点的第二范围 。

    Method and apparatus for automatic recovery from a failed node concurrent maintenance operation
    23.
    发明授权
    Method and apparatus for automatic recovery from a failed node concurrent maintenance operation 失效
    从失败的节点并发维护操作中自动恢复的方法和装置

    公开(公告)号:US07453816B2

    公开(公告)日:2008-11-18

    申请号:US11054288

    申请日:2005-02-09

    IPC分类号: G01R31/08 G06F13/00

    CPC分类号: G06F11/0793 G06F11/0724

    摘要: A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed.If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

    摘要翻译: 本发明提供了一种方法,装置和计算机指令,以便从故障节点并发维护操作中自动恢复。 提供控制逻辑以将第一测试命令发送到新节点的处理器。 如果第一个测试命令成功,则将第二个测试命令发送到所有处理器或其他节点,如果节点被删除。 如果第二个命令成功,则使用添加或删除节点的新配置的拓扑恢复系统操作。 如果响应不正确或发生超时,控制逻辑将恢复到当前模式寄存器的值,并发送第三个测试命令来检查错误。 如果遇到错误,致命的系统注意事项将发送到服务处理器或系统软件。 如果没有错误,则使用先前配置的拓扑恢复系统操作。

    Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system
    25.
    发明授权
    Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system 失效
    用于通过分布式多总线多处理器系统中的数据功能与地址和控制功能的物理分离来控制数据传输的方法和系统

    公开(公告)号:US06725307B1

    公开(公告)日:2004-04-20

    申请号:US09404280

    申请日:1999-09-23

    IPC分类号: G06F100

    摘要: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, e.g. buses that support a high number of data pins, the node controller may be implemented such that the functionality for its address paths and data paths are implemented in physically separate components, chips, or circuitry, such as a node data controller or a node address controller. In this case, commands may be sent from the node address controller to the node data controller to control the flow of data through a node.

    摘要翻译: 提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。 分布式系统结构包含地址交换机,多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备,处理器,I / O代理或相干存储器适配器。 节点控制器从主设备接收命令,与主设备作为另一个主设备或从设备通信,并对从主设备接收的命令进行排队。 由于可能由大型总线引起的引脚限制,例如 支持大量数据引脚的总线,可以实现节点控制器,使得其地址路径和数据路径的功能在物理上分离的组件,芯片或电路中实现,诸如节点数据控制器或节点地址控制器 。 在这种情况下,命令可以从节点地址控制器发送到节点数据控制器,以控制通过节点的数据流。

    Method and system for high speed access to a banked cache memory
    26.
    发明授权
    Method and system for high speed access to a banked cache memory 失效
    用于高速访问存储缓存的方法和系统

    公开(公告)号:US06553463B1

    公开(公告)日:2003-04-22

    申请号:US09436959

    申请日:1999-11-09

    IPC分类号: G06F1200

    摘要: A method and system for high speed data access of a banked cache memory. In accordance with the method and system of the present invention, during a first cycle, in response to receipt of a request address at an access controller, the request address is speculatively transmitted to a banked cache memory, where the speculative transmission has at least one cycle of latency. Concurrently, the request address is snooped in a directory associated with the banked cache memory. Thereafter, during a second cycle the speculatively transmitted request address is distributed to each of multiple banks of memory within the banked cache memory. In addition, the banked cache memory is provided with a bank indication indicating which bank of memory among the multiple banks of memory contains the request address, in response to a bank hit from snooping the directory. Thereafter, data associated with the request address is output from the banked cache memory, in response to the bank indication, such that access time to a high latency remote banked cache memory is minimized.

    摘要翻译: 一种用于高速缓存存储器的高速数据访问的方法和系统。 根据本发明的方法和系统,在第一周期期间,响应于在访问控制器处接收到请求地址,请求地址被推测地发送到存储的高速缓冲存储器,其中推测传输具有至少一个 延迟周期。 同时,请求地址被窥探在与存储的高速缓冲存储器相关联的目录中。 此后,在第二周期期间,推测性发送的请求地址被分配到分组缓存存储器内的多个存储器组中的每一个。 此外,为了响应于窥探目录的银行命中,所述存储体高速缓存存储器具有指示多个存储器组中的存储器组包含请求地址的存储体指示。 此后,响应于存储体指示,从存储的高速缓冲存储器输出与请求地址相关联的数据,使得到高等待时间的远程分组高速缓冲存储器的访问时间被最小化。

    Method and system for communicating information in a network
    27.
    发明授权
    Method and system for communicating information in a network 有权
    用于在网络中传送信息的方法和系统

    公开(公告)号:US06317415B1

    公开(公告)日:2001-11-13

    申请号:US09162317

    申请日:1998-09-28

    IPC分类号: H04L1243

    摘要: A communications system includes a plurality of network nodes including a first node having an interface unit. The interface unit includes a scheduler operable to schedule periodic transmission of a plurality of frames at respective designated times. Each of the plurality of frames includes a plurality of slots. The interface unit also includes an access system operable to designate which of the plurality of slots of a frame are accessible by each of the plurality of nodes and to access the designated slots.

    摘要翻译: 通信系统包括多个网络节点,包括具有接口单元的第一节点。 接口单元包括调度器,其可操作用于在相应的指定时间段调度多个帧的周期性传输。 多个帧中的每一个包括多个时隙。 接口单元还包括可操作以指定帧的多个时隙中的哪一个可由多个节点中的每个节点访问并访问指定时隙的接入系统。

    Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller
    28.
    发明授权
    Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller 有权
    具有多个计算元件的处理器芯片和连接到垂直互连干线的外部I / O接口,通过交叉点总线控制器通信相干信号

    公开(公告)号:US07917730B2

    公开(公告)日:2011-03-29

    申请号:US12060683

    申请日:2008-04-01

    IPC分类号: G06F13/40

    CPC分类号: G06F15/8007

    摘要: A multi-chip processor apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk that communicates information between multiple compute elements situated along the primary interconnect trunk. That multiple processor chip includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of that multiple processor chip. The secondary interconnect trunk intersects the primary interconnect trunk at an intersection at which a bus control element is located. The bus control element includes a primary trunk interface that couples to the primary interconnect trunk at the intersection to enable the bus control element to control on-chip communication among the compute elements via coherency signals on the primary interconnect trunk. The bus control element includes a secondary trunk interface coupled to the secondary interconnect trunk.

    摘要翻译: 多芯片处理器装置在基板上包括多个处理器芯片。 多个处理器芯片中的至少一个包括具有主互连干线的管芯,其在沿着主互连干线位于的多个计算元件之间传送信息。 该多处理器芯片包括可相对于主互连干线垂直定向的次级互连干线。 辅助互连中继线通过多处理器芯片周边的多个I / O接口来传送芯片外的信息。 次互连干线在总线控制元件所在的交点处与主互连干线相交。 总线控制元件包括在交叉点处耦合到主互连干线的主干接口,以使得总线控制元件能够通过主互连干线上的相干信号来控制计算元件之间的片上通信。 总线控制元件包括耦合到辅助互连主干的辅助中继接口。

    Data processing system and processing unit having an address-based launch governor
    30.
    发明授权
    Data processing system and processing unit having an address-based launch governor 失效
    数据处理系统和处理单元具有基于地址的发射调速器

    公开(公告)号:US07809004B2

    公开(公告)日:2010-10-05

    申请号:US12102133

    申请日:2008-04-14

    IPC分类号: H04L12/28

    摘要: A data processing system includes an interconnect fabric, a protected resource having a plurality of banks each associated with a respective one of a plurality of address sets, a snooper that controls access to the resource, one or more masters that initiate requests, and interconnect logic coupled to the one or more masters and to the interconnect fabric. The interconnect logic regulates a rate of delivery to the snooper via the interconnect fabric of requests that target any one the plurality of banks of the protected resource.

    摘要翻译: 数据处理系统包括互连结构,受保护资源具有多个存储体,每个存储体各自与多个地址集合中的相应一个地址集相关联,控制对资源的访问的监听器,发起请求的一个或多个主站和互连逻辑 耦合到一个或多个主器件和互连结构。 互连逻辑通过针对受保护资源的多个组中的任一个的请求的互连结构来调节到窥探者的传送速率。