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    Substitute redundant memory
    22.
    发明授权
    Substitute redundant memory 有权

    公开(公告)号：US11119857B2

    公开(公告)日：2021-09-14

    申请号：US14031031

    申请日：2013-09-18

    Applicant: Dipak K Sikdar ,  Rajesh Chopra

    Inventor： Dipak K Sikdar ,  Rajesh Chopra

    IPC: G06F11/10 ,  G11C29/44 ,  G11C29/42 ,  G06F11/20 ,  G11C29/06 ,  G11C29/12 ,  G11C29/50 ,  G11C29/00

    Abstract: An integrated circuit (IC) chip for transparent and in-service or production repair of single to multiple memory cell defects in a word during the datapath transit of the word between core memory to the interface of the IC via capturing an accurate bit from a word during a write access to a known defective memory address, and by substituting in a non-defective bit into the word during a read access from a known defective memory address. The IC includes: address matching circuit (CAM), a random access memory (RAM) of substitute memory cells containing accurate associated bit data and bit location in word of defect, and data selection circuitry (MUXs) coupled together.

    System and method for application configuration comparison and reuse
    24.
    发明授权
    System and method for application configuration comparison and reuse 失效
    用于应用程序配置比较和重用的系统和方法

    公开(公告)号：US08495620B2

    公开(公告)日：2013-07-23

    申请号：US12043440

    申请日：2008-03-06

    Applicant: Rajesh Chopra ,  SweeFen Goh ,  Richard Thomas Goodwin ,  Anca-Andreea Ivan ,  Stephen K. Kibby ,  Rakesh Mohan ,  Igor Naumov ,  Thomas Dean Rosinski ,  George A. Schroeder

    Inventor： Rajesh Chopra ,  SweeFen Goh ,  Richard Thomas Goodwin ,  Anca-Andreea Ivan ,  Stephen K. Kibby ,  Rakesh Mohan ,  Igor Naumov ,  Thomas Dean Rosinski ,  George A. Schroeder

    IPC: G06F9/445 ,  G06F9/44

    CPC classification number: G06F8/71 ,  G06Q10/06

    Abstract: A system and method allow a user to extract the set of customizations performed on an application and use these to estimate the time and effort and cost of (a) migrating to a new version of the application and/or (b) consolidating systems. The user can browse the extracted data and select configuration elements for re-use. After downloading the one or more configurations and comparing them, the user selects elements of the configurations for re-use. The first step is to scan one or more application systems and extract the configuration data using a surveyor. The method according to the invention automatically identifies configuration differences. The user then selects configuration elements for re-use. A graphic user interface (GUI) can be provided which allows the user to make these selections by dragging and dropping selected elements to a “To Be” configuration. The selected configurations are then uploaded and installed on an instance of the application.

    Abstract translation: 系统和方法允许用户提取在应用程序上执行的一组定制，并使用它们来估计（a）迁移到新版本的应用程序和/或（b）合并系统的时间和精力和成本。 用户可以浏览提取的数据并选择配置元素以供重复使用。 下载一个或多个配置并对其进行比较后，用户选择配置的元素以供重复使用。 第一步是扫描一个或多个应用系统并使用测量仪提取配置数据。 根据本发明的方法自动识别配置差异。 然后用户选择配置元素以供重用。 可以提供图形用户界面（GUI），其允许用户通过将所选择的元素拖放到“To Be”配置来进行这些选择。 所选配置然后上传并安装在应用程序的实例上。

    IDENTIFICATION OF GENE EXPRESSION AS A PREDICTIVE BIOMARKER FOR LKB1 STATUS
    25.
    发明申请
    IDENTIFICATION OF GENE EXPRESSION AS A PREDICTIVE BIOMARKER FOR LKB1 STATUS 审中-公开
    基因表达的鉴定作为LKB1状态的预测生物标记

    公开(公告)号：US20130158023A1

    公开(公告)日：2013-06-20

    申请号：US13701224

    申请日：2012-08-02

    Applicant: Yuhong L. Ning ,  Weiming Xu ,  Rajesh Chopra ,  Peter Worland ,  Shuichan Xu

    Inventor： Yuhong L. Ning ,  Weiming Xu ,  Rajesh Chopra ,  Peter Worland ,  Shuichan Xu

    IPC: A61K31/5377 ,  A61K31/437 ,  A61K31/498 ,  C12Q1/68 ,  A61K31/53

    CPC classification number: A61K31/5377 ,  A61K31/437 ,  A61K31/498 ,  A61K31/53 ,  C12Q1/6886 ,  C12Q2600/106 ,  C12Q2600/158

    Abstract: Provided herein are methods for predicting the LKB1 status of a patient or a biological sample, comprising the measurement of particular gene expression levels relative to a set of reference levels that represent the gene expression level of a biological wild-type sample without LKB1 gene or protein loss or mutation and the gene expression level of a reference sample with LKB1 gene or protein loss or mutation. Further provided herein are methods for treating and/or preventing a cancer or a tumor syndrome in a patient, comprising administering an effective amount of a TOR kinase inhibitor to a patient having cancer or a tumor syndrome, characterized by particular gene expression levels.

    Abstract translation: 本文提供了用于预测患者或生物样品的LKB1状态的方法，其包括相对于代表没有LKB1基因或蛋白质的生物野生型样品的基因表达水平的一组参考水平的特定基因表达水平的测量 损失或突变，以及具有LKB1基因或蛋白质丢失或突变的参考样品的基因表达水平。 本文还提供了用于治疗和/或预防患者的癌症或肿瘤综合征的方法，其包括以具有特定基因表达水平为特征的患有癌症或肿瘤综合征的患者施用有效量的TOR激酶抑制剂。

    Method for loading instructions or data into a locked way of a cache memory
    26.
    发明授权
    Method for loading instructions or data into a locked way of a cache memory 失效
    将指令或数据加载到高速缓冲存储器的锁定方式的方法

    公开(公告)号：US06629207B1

    公开(公告)日：2003-09-30

    申请号：US09410693

    申请日：1999-10-01

    Applicant: Shinichi Yoshioka ,  Rajesh Chopra ,  Atsushi Hasegawa

    Inventor： Shinichi Yoshioka ,  Rajesh Chopra ,  Atsushi Hasegawa

    IPC: G06F1200

    CPC classification number: G06F12/0864 ,  G06F12/1045 ,  G06F12/126

    Abstract: Methods of operating an instruction cache memory in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having locations in a memory space. The entries of the instruction cache memory include a number of sets (nsets), where each of the sets comprise a number of ways (nways). One or more first instructions may be executed to load one or more instructions into a first way of the instruction cache memory. One or more second instructions may be executed to lock the first way of the instruction cache memory. A sequence of instructions may be executed including the one or more instructions loaded in the first way of the instruction cache memory, and it may be predetermined that the one or more instructions loaded in the first way of the instruction cache memory will executed without retrieving the one or more instructions from the memory during execution of the sequence of instructions. The instruction cache memory may be controlled by a control register in a register space separate from the memory space. The one or more second instructions may include a PUT instruction for writing information to the control register that controls the locking of the instruction cache memory. The sequence of instructions including the one or more instructions loaded in the first way of the instruction cache memory may be executed in a manner where it is predetermined that the one or more instructions loaded in the first way of the instruction cache memory will be executed during execution of the sequence of instructions without a cache miss.

    Abstract translation: 公开了在数据处理系统中操作指令高速缓冲存储器的方法。 数据处理系统执行指令并存储并从存储器空间中具有位置的存储器接收数据。 指令高速缓冲存储器的条目包括多个集合（nsets），其中每个集合包括多个方式（不管）。 可以执行一个或多个第一指令以将一个或多个指令加载到指令高速缓冲存储器的第一方式中。 可以执行一个或多个第二指令以锁定指令高速缓冲存储器的第一路。 可以执行指令序列，包括以指令高速缓存存储器的第一种方式加载的一个或多个指令，并且可以预先确定以指令高速缓冲存储器的第一种方式加载的一个或多个指令将不执行 在执行指令序列期间来自存储器的一个或多个指令。 指令高速缓存存储器可以由与存储器空间分开的寄存器空间中的控制寄存器来控制。 一个或多个第二指令可以包括用于向控制寄存器写入信息以控制指令高速缓冲存储器的锁定的PUT指令。 包括以指令高速缓冲存储器的第一种方式加载的一个或多个指令的指令序列可以以预定的方式执行，即以指令高速缓冲存储器的第一种方式加载的一个或多个指令将在 没有高速缓存未命中的指令序列的执行。

    Write buffer with burst capability
    27.
    发明授权
    Write buffer with burst capability 失效
    具有突发能力的写缓冲区

    公开(公告)号：US06496905B1

    公开(公告)日：2002-12-17

    申请号：US09410555

    申请日：1999-10-01

    Applicant: Shinichi Yoshioka ,  Hsuan-Wen Wang ,  Rajesh Chopra ,  Jun-Wen Tsong

    Inventor： Shinichi Yoshioka ,  Hsuan-Wen Wang ,  Rajesh Chopra ,  Jun-Wen Tsong

    IPC: G06F1200

    CPC classification number: G06F12/0879

    Abstract: Methods and an apparatus for buffering write operations are disclosed. In one embodiment, a processing system bursts data to a bus. The processing system includes a memory cache, a write buffer unit, and a control unit. The memory cache produces an address and data. Included in the write buffer unit are a plurality of data locations coupled to the memory cache. The control unit directs the first data to any of the plurality of data locations.

    Abstract translation: 公开了用于缓冲​​写入操作的方法和装置。 在一个实施例中，处理系统将数据突发到总线。 处理系统包括存储器高速缓存，写入缓冲器单元和控制单元。 内存缓存生成一个地址和数据。 包括在写入缓冲器单元中的是耦合到存储器高速缓存的多个数据位置。 控制单元将第一数据引导到多个数据位置中的任一个。

    Cache memory store buffer
    28.
    发明授权
    Cache memory store buffer 有权
    缓存存储器缓冲区

    公开(公告)号：US06434665B1

    公开(公告)日：2002-08-13

    申请号：US09410678

    申请日：1999-10-01

    Applicant: David Shepherd ,  Rajesh Chopra

    Inventor： David Shepherd ,  Rajesh Chopra

    IPC: G06F1100

    CPC classification number: G06F12/0855

    Abstract: Methods and an apparatus for storing information in a processing device with flexible security are disclosed. In one embodiment, an apparatus processes back-to-back write and read operations without stalling the processor. A cache memory subsystem buffers write operations between a central processing unit (CPU) and the cache memory subsystem. Included in the cache memory subsystem are a tag memory, a data memory and a store buffer. The store buffer is coupled to both the data memory and the tag memory. Additionally, the store buffer stores a write operation.

    Abstract translation: 公开了一种在具有灵活安全性的处理设备中存储信息的方法和装置。 在一个实施例中，设备在不停止处理器的情况下处理背靠背写入和读取操作。 缓存存储器子系统缓冲中央处理单元（CPU）和高速缓冲存储器子系统之间的写入操作。 高速缓冲存储器子系统中包括标签存储器，数据存储器和存储缓冲器。 存储缓冲器耦合到数据存储器和标签存储器。 另外，存储缓冲器存储写入操作。

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