中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

35 records (took 0.021 seconds)

    Cache memory store buffer
    1.
    发明授权
    Cache memory store buffer 有权
    缓存存储器缓冲区

    公开(公告)号：US06434665B1

    公开(公告)日：2002-08-13

    申请号：US09410678

    申请日：1999-10-01

    Applicant: David Shepherd ,  Rajesh Chopra

    Inventor： David Shepherd ,  Rajesh Chopra

    IPC: G06F1100

    CPC classification number: G06F12/0855

    Abstract: Methods and an apparatus for storing information in a processing device with flexible security are disclosed. In one embodiment, an apparatus processes back-to-back write and read operations without stalling the processor. A cache memory subsystem buffers write operations between a central processing unit (CPU) and the cache memory subsystem. Included in the cache memory subsystem are a tag memory, a data memory and a store buffer. The store buffer is coupled to both the data memory and the tag memory. Additionally, the store buffer stores a write operation.

    Abstract translation: 公开了一种在具有灵活安全性的处理设备中存储信息的方法和装置。 在一个实施例中，设备在不停止处理器的情况下处理背靠背写入和读取操作。 缓存存储器子系统缓冲中央处理单元（CPU）和高速缓冲存储器子系统之间的写入操作。 高速缓冲存储器子系统中包括标签存储器，数据存储器和存储缓冲器。 存储缓冲器耦合到数据存储器和标签存储器。 另外，存储缓冲器存储写入操作。

    Microprocessor having improved memory management unit and cache memory
    2.
    发明授权
    Microprocessor having improved memory management unit and cache memory 失效

    公开(公告)号：US06598128B1

    公开(公告)日：2003-07-22

    申请号：US09410567

    申请日：1999-10-01

    Applicant: Shinich Yoshioka ,  David Shepherd ,  Rajesh Chopra

    Inventor： Shinich Yoshioka ,  David Shepherd ,  Rajesh Chopra

    IPC: G06F1200

    CPC classification number: G06F12/1063 ,  G06F12/0835

    Abstract: Methods of maintaining cache coherency of a virtual cache memory system in a data processing system are disclosed. The entries of the virtual cache memory include physical address information and logical address information. A memory access operation may be initiated on one or more predetermined memory locations based on physical address information. A determination may be made if the memory access operation may involve cache coherent memory. If the memory access operation may involve cache coherent memory, then a cache coherency command may be issued that contains physical address information of the memory access operation. Based on the cache coherency command and the physical address information, a determination may be made if there is a match between the physical address information of the memory access operation and the physical address information stored in the virtual cache. If there is a match, then a determination may be made whether data associated with the particular entry of the virtual cache memory is dirty. If the data associated with the particular entry of the virtual cache memory is dirty, then a write back operation may be initiated, and data in the particular entry of the virtual cache memory may be written to memory. A command may then be issued that indicates that the virtual cache memory and the memory locations of the memory access operation are cohered, and the memory access operation may be completed. A determination also may be made whether the memory access operation is a write operation. If the memory access operation is a write operation, then the particular entry of the virtual cache memory may be invalidated. The virtual cache memory may be included in a single chip microprocessor, and a device external to the single chip microprocessor may initiate the memory access operation. A circuit that bridges between the external device and an internal bus may receive a command from the external device to initiate the memory access operation.

    Microprocessor having improved memory management unit and cache memory
    3.
    发明授权
    Microprocessor having improved memory management unit and cache memory 失效

    公开(公告)号：US06591340B2

    公开(公告)日：2003-07-08

    申请号：US10166503

    申请日：2002-06-10

    Applicant: Rajesh Chopra ,  Shinichi Yoshioka ,  Mark Debbage ,  David Shepherd

    Inventor： Rajesh Chopra ,  Shinichi Yoshioka ,  Mark Debbage ,  David Shepherd

    IPC: G06F1200

    CPC classification number: G06F9/383 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3802 ,  G06F12/0888 ,  G06F12/1063 ,  G06F12/126 ,  G06F12/145

    Abstract: Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted. If the memory access operation is not permitted by the permission information of the particular entry of the virtual cache memory, then the translation lookaside buffer may be accessed based on the logical address information of the particular entry of the virtual cache memory. If there is a match between the logical address information of the particular entry of the virtual cache memory and the logical address information of a particular entry of the translation lookaside buffer, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the translation lookaside buffer as to whether the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer. If the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer, then the permission information of the particular entry of the virtual cache memory may be updated based on the permission information of the particular entry of the translation lookaside buffer and the memory access operation may be completed.

    Microprocessor having improved memory management unit and cache memory
    4.
    发明授权
    Microprocessor having improved memory management unit and cache memory 失效

    公开(公告)号：US06412043B1

    公开(公告)日：2002-06-25

    申请号：US09410506

    申请日：1999-10-01

    Applicant: Rajesh Chopra ,  Shinichi Yoshioka ,  Mark Debbage ,  David Shepherd

    Inventor： Rajesh Chopra ,  Shinichi Yoshioka ,  Mark Debbage ,  David Shepherd

    IPC: G06F1200

    CPC classification number: G06F9/383 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3802 ,  G06F12/0888 ,  G06F12/1063 ,  G06F12/126 ,  G06F12/145

    Abstract: Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted. If the memory access operation is not permitted by the permission information of the particular entry of the virtual cache memory, then the translation lookaside buffer may be accessed based on the logical address information of the particular entry of the virtual cache memory. If there is a match between the logical address information of the particular entry of the virtual cache memory and the logical address information of a particular entry of the translation lookaside buffer, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the translation lookaside buffer as to whether the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer. If the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer, then the permission information of the particular entry of the virtual cache memory may be updated based on the permission information of the particular entry of the translation lookaside buffer and the memory access operation may be completed.

    Aligning load/store data with big/little endian determined rotation distance control
    7.
    发明申请
    Aligning load/store data with big/little endian determined rotation distance control 有权
    对齐加载/存储数据与大/小端确定旋转距离控制

    公开(公告)号：US20050071583A1

    公开(公告)日：2005-03-31

    申请号：US10984271

    申请日：2004-11-08

    Applicant: David Shepherd

    Inventor： David Shepherd

    IPC: G06F9/34 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F12/00 ,  G06F12/04

    CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F9/3816 ,  G06F9/383

    Abstract: The present invention relates generally to microprocessor or microcontroller architecture, and particularly to an architecture structured to handle unaligned memory references. A method is disclosed for loading unaligned data stored in several memory locations, including a step of loading a first part of the unaligned data into a first storage location and rotating the first part from a first position to a second position in the first memory location. Next a second part of the unaligned data is loaded into a second storage location and rotated from one position to another position. Then the first storage location is combined with the second storage location using a logical operation into a result storage location. The storage locations may be, for example, 64-bit registers. The logical operation may be a bit-wise OR operation. The method may optionally include, performing masking, zero-extending and/or sign extending operations on the first storage location, when the first part of the unaligned data is in the second position of the first storage location.

    Abstract translation: 本发明一般涉及微处理器或微控制器架构，特别涉及一种结构化以处理未对齐的存储器引用的架构。 公开了一种用于加载存储在多个存储器位置中的未对齐数据的方法，包括将未对齐数据的第一部分加载到第一存储位置并将第一部分从第一位置旋转到第一存储器位置中的第二位置的步骤。 接下来，未对齐数据的第二部分被加载到第二存储位置并且从一个位置旋转到另一个位置。 然后，使用逻辑操作将第一存储位置与第二存储位置组合到结果存储位置。 存储位置可以是例如64位寄存器。 逻辑运算可以是逐位或运算。 当未对齐数据的第一部分处于第一存储位置的第二位置时，该方法可以可选地包括对第一存储位置执行掩蔽，零扩展和/或符号扩展操作。

    Feeder for centrifugal apparatus
    9.
    发明授权
    Feeder for centrifugal apparatus 失效
    离心设备进料器

    公开(公告)号：US4534754A

    公开(公告)日：1985-08-13

    申请号：US615273

    申请日：1984-05-30

    Applicant: David Shepherd

    Inventor： David Shepherd

    IPC: B03B5/00 ,  B04B5/00 ,  B04B11/02 ,  B01D45/12 ,  B04B11/00

    CPC classification number: B03B5/00 ,  B04B11/02 ,  B04B5/00 ,  B04B2005/045

    Abstract: An apparatus and method for providing an accurately regulated flow of liquid medium to a device mounted in or on a rotor of a centrifuge, comprises a scoop on the rotor having a mouth opening forwards in the direction of rotation, with a duct connecting the mouth to the device; the liquid medium being projected as a jet into the path of the rotating scoop so that the mouth chops out a mid-portion of the jet during each revolution, and feeds it to the device. Rotation rates are high, typically 50,000 rpm for devices like liquid flow density balances for mass detection, but may be less and/or variable with SFFF devices.

    Abstract translation: 一种用于向安装在离心机的转子中或其上的设备提供精确调节的液体介质流的装置和方法，包括转子上的勺子，其具有在旋转方向上向前开口的口， 装置; 液体介质以喷射的方式投射到旋转勺的路径中，使得在每次旋转期间嘴部剔除喷射的中间部分，并将其馈送到装置。 旋转速率高，对于质量检测的液体流量密度平衡等设备，通常为50,000 rpm，但SFFF装置可能较少和/或变化。

Patent Agency Ranking