公开(公告)号：US06842847B2

公开(公告)日：2005-01-11

申请号：US10268744

申请日：2002-10-10

Applicant: Ravi Kumar Arimilli ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  Derek Edward Williams

IPC: G06F9/30 ,  G06F12/00 ,  G06F12/08 ,  G06F12/14

CPC classification number: G06F12/084 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F12/1433 ,  Y10S707/99938

Abstract: A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing a plurality of promotion bit fields. The first processor executes a single acquisition instruction to concurrently acquire a plurality of promotion bit fields exclusive of at least the second processor. In response to execution of the acquisition instruction, the first processor receives an indication of success or failure of the acquisition instruction, wherein the indication indicates success of the acquisition instruction if all of the plurality of promotion bit fields were concurrently acquired by the first processor and indicates failure of the acquisition instruction if fewer than all of the plurality of promotion bit fields were acquired by the first processor.

Abstract translation: 多处理器数据处理系统包括耦合到互连的第一和第二处理器以及包含多个提升位字段的全局推广设备。 第一处理器执行单个采集指令以同时获取排斥至少第二处理器的多个升级位字段。 响应于所述获取指令的执行，所述第一处理器接收所述获取指令的成功或失败的指示，其中如果所述多个提升位字段是由所述第一处理器同时获取的，则所述指示指示所述获取指令的成功，以及 指示如果所述第一处理器获取的所述多个提升位字段中的少于全部，则所述获取指令失败。

公开(公告)号：US06829698B2

公开(公告)日：2004-12-07

申请号：US10268727

申请日：2002-10-10

Applicant: Ravi Kumar Arimilli ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  Derek Edward Williams

IPC: G06F946

CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F12/0811 ,  G06F12/0815 ,  Y10S707/99938 ,  Y10S707/99952

Abstract: A data processing system includes a global promotion facility and a plurality of processors coupled by an interconnect. In response to execution of an acquisition instruction by a first processor among the plurality of processors, the first processor transmits an address-only operation on the interconnect to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor among the plurality of processors. In response to receipt of a combined response for the address-only operation representing a collective response of others of the plurality of processors to the address-only operation, the first processor determines whether or not acquisition of the promotion bit field was successful by reference to the combined response.

Abstract translation: 数据处理系统包括全球推广设施和通过互连耦合的多个处理器。 响应于多个处理器中的第一处理器执行获取指令，第一处理器在互连上发送仅地址操作，以在全球推广设备之内获取不包括至少第二处理器的促销位字段 多个处理器。 响应于接收到仅地址操作的组合响应，其表示多个处理器中的其他处理器的集合响应到仅地址操作，则第一处理器通过参考获取促销位字段的获取是否成功 综合反应。

公开(公告)号：US06826655B2

公开(公告)日：2004-11-30

申请号：US10216632

申请日：2002-08-08

Applicant: Ravi Kumar Arimilli ,  Guy Lynn Guthrie

Inventor： Ravi Kumar Arimilli ,  Guy Lynn Guthrie

IPC: G06F1208

CPC classification number: G06F12/0811

Abstract: A symmetric multiprocessor data processing system having an apparatus for imprecisely tracking cache line inclusivity of a higher level cache is disclosed. The symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units is associated with a level one cache memory. All the level one cache memories are associated with an imprecisely inclusive level two cache memory. The imprecisely inclusive level two cache memory includes a tracking means for imprecisely tracking cache line inclusivity of the level one cache memories. The tracking means includes a last_processor_to_store field and a more_than_two_loads field per cache line. When the more_than_two_loads field is asserted, except for a specific cache line in the level one cache memory associated with the processor indicated in the last_processor_to_store field, all cache lines within the level one cache memories that shared identical information with that specific cache line are invalidated.

Abstract translation: 公开了一种对称多处理器数据处理系统，其具有用于不精确地跟踪高级缓存的高速缓存行包含性的装置。 对称多处理器数据处理系统包括多个处理单元。 每个处理单元与一级缓存存储器相关联。 所有一级缓存存储器与不精确包含的两级缓存存储器相关联。 不精确包含的两级缓存存储器包括用于不精确地跟踪一级高速缓存存储器的高速缓存行包容性的跟踪装置。 跟踪装置包括每个高速缓存行的last_processor_to_store字段和more_than_two_loads字段。 当more_than_two_loads字段被断言时，除了与last_processor_to_store字段中指示的处理器相关联的一级高速缓冲存储器中的特定高速缓存行之外，与该特定高速缓存行共享相同信息的一级缓存存储器内的所有高速缓存行无效。

公开(公告)号：US06782456B2

公开(公告)日：2004-08-24

申请号：US09915432

申请日：2001-07-26

Applicant: Ravi Kumar Arimilli ,  George William Daly, Jr. ,  Paul K. Umbarger

Inventor： Ravi Kumar Arimilli ,  George William Daly, Jr. ,  Paul K. Umbarger

IPC: G06F1200

CPC classification number: G06F12/0835 ,  G06F13/28

Abstract: A method and data processing system that supports pipelining of Input/Output (I/O) DMA Write transactions. An I/O processor's operational protocol is provided with a pair of instructions/commands that are utilized to complete a DMA Write operation. The instructions are DMA_Write_No_Data and DMA_Write_With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire ownership of a cache line that is to be written. The ownership of the cache line is marked by a weak DMA state, which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations. When each preceding DMA Write operation has completed or each corresponding DMA_Write_No_Data operation has been placed in a DMA Exclusive state, then the weak DMA state is changed to a DMA Exclusive state, which forces a retry of snooped operations until the write transaction to memory is completed. In this way, DMA Writes that are provided sequentially may be issued in a parallel manner on the system bus and their corresponding DMA_Write_No_Data operations may be completed in any order, but cannot be made DMA Exclusive unless the above conditions are satisfied. Further, once a DMA Exclusive state is acquired, a DMA_Write_With_Data may be issued for each of the sequential DMA Write operations in the DMA Exclusive state. The DMA_Write_With_Data may then be completed out-of-order with respect to each other. However, the system processor is sent the completion messages in the sequential order of the DMA Write operations, thus adhering to the processor requirements for ordered operations while providing fully-pipelined (parallel) execution of the DMA transactions.

Abstract translation: 支持输入/输出（I / O）DMA写入事务流水线的方法和数据处理系统。 I / O处理器的操作协议提供有一对用于完成DMA写操作的指令/命令。 指令是DMA_Write_No_Data和DMA_Write_With_Data。 DMA_Write_No_Data是用于获取要写入的高速缓存行的所有权的系统总线上的仅地址操作。 高速缓存行的所有权标记为弱DMA状态，这表示高速缓存行被保留用于写入内存，但高速缓存行不能强制重试侦听操作。 当前一个DMA写操作完成或每个相应的DMA_Write_No_Data操作已经被置于DMA独占状态时，则弱DMA状态被改变为DMA独占状态，这迫使重复执行窥探操作，直到对存储器的写事务完成 。 以这种方式，顺序提供的DMA写入可以以并行方式发布在系统总线上，并且它们相应的DMA_Write_No_Data操作可以以任何顺序完成，但是除非满足上述条件，否则不能进行DMA独占。 此外，一旦获取DMA独占状态，可以在DMA独占状态中为每个顺序DMA写操作发出DMA_Write_With_Data。 然后可以相对于彼此完成无序的DMA_Write_With_Data。 然而，系统处理器按照DMA写操作的顺序发送完成消息，因此在提供完全流水线（并行）DMA事务的执行的同时，遵循处理器对有序操作的要求。

公开(公告)号：US06779086B2

公开(公告)日：2004-08-17

申请号：US09978363

申请日：2001-10-16

Applicant: Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

IPC: G06F1200

CPC classification number: G06F12/0831 ,  G06F12/0817

Abstract: A multiprocessor data processing system comprising, in addition to a first and second processor having an respective first and second cache and a main cache directory affiliated with the first processor's cache, a secondary cache directory of the first cache, which contains a subset of cache line addresses from the main cache directory corresponding to cache lines that are in a first or second coherency state, where the second coherency state indicates to the first processor that requests issued from the first processor for a cache line whose address is within the secondary directory should utilize super-coherent data currently available in the first cache and should not be issued on the system interconnect. Additionally, the cache controller logic includes a clear on barrier flag (COBF) associated with the secondary directory, which is set whenever an operation of the first processor is issued to said system interconnect. If a barrier instruction is received by the first processor while the COBF is set, the contents of the secondary directory are immediately flushed and the cache lines are tagged with an invalid state.

Abstract translation: 一种多处理器数据处理系统，除了具有相应的第一和第二高速缓存以及隶属于第一处理器的高速缓存的主缓存目录的第一处理器和第二处理器之外，还包括第一高速缓存的副高速缓存目录，其包含高速缓存行的子集 来自对应于处于第一或第二相关性状态的高速缓存行的主缓存目录的地址，其中第二一致性状态向第一处理器指示从第一处理器发出的对于地址在次目录内应该利用的高速缓存行的请求 超级相干数据目前在第一个缓存中可用，不应在系统互连上发布。 此外，高速缓存控制器逻辑包括与副目录相关联的清除屏障标志（COBF），其随着第一处理器的操作被发布到所述系统互连而被设置。 如果在设置COBF时由第一处理器接收到屏障指令，则立即刷新副目录的内容，并将高速缓存行标记为无效状态。

公开(公告)号：US06763435B2

公开(公告)日：2004-07-13

申请号：US09978355

申请日：2001-10-16

Applicant: Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

IPC: G06F1314

CPC classification number: G06F12/0831

Abstract: A method for improving performance of a multiprocessor data processing system comprising snooping a request for data held within a shared cache line on a system bus of the data processing system whose cache contains an updated copy of the shared cache line, and responsive to a snoop of the request by the second processor, issuing a first response on the system bus indicating to the requesting processor that the requesting processor may utilize data currently stored within the shared cache line of a cache of the requesting processor. When the request is snooped by the second processor and the second processor decides to release a lock on the cache line to the requesting processor, the second processor issues a second response on the system bus indicating that the first processor should utilize new/coherent data and then the second processor releases the lock to the first processor.

Abstract translation: 一种用于提高多处理器数据处理系统的性能的方法，包括：窥探在所述数据处理系统的系统总线上的共享高速缓存行中保存的数据的请求，所述数据处理系统的高速缓存包含所述共享高速缓存行的更新副本，并响应于所述 第二处理器的请求，在系统总线上发出第一响应，向请求处理器指示请求处理器可以利用当前存储在请求处理器的高速缓存的共享高速缓存行中的数据。 当请求被第二处理器窥探并且第二处理器决定释放到请求处理器的高速缓存行上的锁时，第二处理器在系统总线上发出指示第一处理器应该利用新的/相干数据的第二响应， 那么第二处理器将锁定释放到第一处理器。

公开(公告)号：US06763434B2

公开(公告)日：2004-07-13

申请号：US09752947

申请日：2000-12-30

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Derek Edward Williams

IPC: G06F1200

CPC classification number: G06F12/0831

Abstract: Disclosed herein are a data processing system and method of operating a data processing system that arbitrate between conflicting requests to modify data cached in a shared state and that protect ownership of the cache line granted during such arbitration until modification of the data is complete. The data processing system includes a plurality of agents coupled to an interconnect that supports pipelined transactions. While data associated with a target address are cached at a first agent among the plurality of agents in a shared state, the first agent issues a transaction on the interconnect. In response to snooping the transaction, a second agent provides a snoop response indicating that the second agent has a pending conflicting request and a coherency decision point provides a snoop response granting the first agent ownership of the data. In response to the snoop responses, the first agent is provided with a combined response representing a collective response to the transaction of all of the agents that grants the first agent ownership of the data. In response to the combined response, the first agent is permitted to modify the data.

Abstract translation: 这里公开了一种数据处理系统和方法，该数据处理系统和方法在数据处理系统之间进行仲裁，以便在冲突的请求之间进行仲裁，以修改在共享状态下缓存的数据，并保护在此类仲裁期间授予的高速缓存行的所有权，直到数据修改完成。 数据处理系统包括耦合到支持流水线交易的互连的多个代理。 虽然与目标地址相关联的数据在共享状态的多个代理之间的第一代理处被高速缓存，但第一代理在互连上发布事务。 响应于窥探事务，第二代理提供窥探响应，指示第二代理具有待决冲突请求，并且一致性决策点提供准备数据的第一代理所有权的窥探响应。 响应于窥探响应，向第一代理提供组合的响应，其表示对授予数据的第一代理所有权的所有代理的交易的集体响应。 响应于组合的响应，允许第一代理修改数据。

公开(公告)号：US06760809B2

公开(公告)日：2004-07-06

申请号：US09885992

申请日：2001-06-21

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr.

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr.

IPC: G06F1200

CPC classification number: G06F12/0813 ,  G06F12/0817 ,  G06F12/0831

Abstract: A non-uniform memory access (NUMA) computer system and associated method of operation are disclosed. The NUMA computer system includes at least a remote node and a home node coupled to an interconnect. The remote node contains at least one processing unit coupled to a remote system memory, and the home node contains at least a home system memory. To reduce access latency for data from other nodes, a portion of the remote system memory is allocated as a remote memory cache containing data corresponding to data resident in the home system memory. In one embodiment, access bandwidth to the remote memory cache is increased by distributing the remote memory cache across multiple system memories in the remote node.

Abstract translation: 公开了一种非均匀存储器访问（NUMA）计算机系统及其相关操作方法。 NUMA计算机系统至少包括耦合到互连的远程节点和家庭节点。 远程节点包含耦合到远程系统存储器的至少一个处理单元，并且家庭节点至少包含家用系统存储器。 为了减少来自其他节点的数据的访问延迟，远程系统存储器的一部分被分配为包含对应于驻留在家庭系统存储器中的数据的数据的远程存储器高速缓存。 在一个实施例中，通过在远程节点中的多个系统存储器上分发远程存储器高速缓存来增加对远程存储器高速缓存的访问带宽。

公开(公告)号：US06691220B1

公开(公告)日：2004-02-10

申请号：US09588608

申请日：2000-06-06

Applicant: Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

Inventor： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

IPC: G06F900

CPC classification number: G06F9/3842 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3859

Abstract: A method of operation within a processor that permits load instructions following barrier instructions in an instruction sequence to be issued speculatively. The barrier instruction is executed and while the barrier operation is pending, a load request associated with the load instruction is speculatively issued. A speculation flag is set to indicate the load instruction was speculatively issued. The flag is reset when an acknowledgment of the barrier operation is received. Data that is returned before the acknowledgment is received is temporarily held, and the data is forwarded to the register and/or execution unit of the processor only after the acknowledgment is received. If a snoop invalidate is detected for the speculatively issued load request before the barrier operation completes, the data is discarded and the load request is re-issued.

Abstract translation: 一种处理器内的操作方法，其允许按照指令序列中的障碍指令之后的加载指令进行推测。 屏障指令被执行，并且当屏障操作正在等待时，推测地发出与加载指令相关联的加载请求。 设置了一个猜测标志来指示加载指令被推测发出。 当接收到屏障操作的确认时，该标志被复位。 在接收到确认之前返回的数据被暂时保留，并且仅在接收到确认之后将数据转发到处理器的寄存器和/或执行单元。 如果在屏障操作完成之前，对于推测发出的负载请求检测到窥探无效，则丢弃数据并重新发出加载请求。

公开(公告)号：US06658539B2

公开(公告)日：2003-12-02

申请号：US09978353

申请日：2001-10-16

Applicant: Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

IPC: G06F1200

CPC classification number: G06F12/0831 ,  G06F12/084

Abstract: A method for improving performance of a multiprocessor data processing system having processor groups with shared caches. When a processor within a processor group that shares a cache snoops a modification to a shared cache line in a cache of another processor that is not within the processor group, the coherency state of the shared cache line within the first cache is set to a first coherency state that indicates that the cache line has been modified by a processor not within the processor group and that the cache line has not yet been updated within the group's cache. When a request for the cache line is later issued by a processor, the request is issued to the system bus or interconnect. If a received response to the request indicates that the processor should utilize super-coherent data, the coherency state of the cache line is set to a processor-specific super coherency state. This state indicates that subsequent requests for the cache line by the first processor should be provided said super-coherent data, while a subsequent request for the cache line by a next processor in the processor group that has not yet issued a request for the cache line on the system bus, may still go to the system bus to request the cache line. The individualized, processor-specific super coherency states are individually set but are usually changed to another coherency state (e.g., Modified or Invalid) as a group.

Abstract translation: 一种用于改善具有处理器组与共享高速缓存的多处理器数据处理系统的性能的方法。 当共享缓存的处理器组内的处理器窥探在处理器组内的另一处理器的高速缓存中的共享高速缓存线的修改时，第一高速缓存内的共享高速缓存行的一致性状态被设置为第一 指示高速缓存行已被处理器组内的处理器修改并且高速缓存行尚未在组的高速缓存内更新的一致性状态。 当稍后由处理器发出对高速缓存行的请求时，该请求被发布到系统总线或互连。 如果对该请求的接收到的响应指示处理器应该使用超相干数据，则高速缓存行的一致性状态被设置为处理器特定的超一致性状态。 该状态指示应该为所述超相干数据提供由第一处理器对高速缓存行的后续请求，而处理器组中尚未发出对高速缓存行请求的下一个处理器对高速缓存行的后续请求 在系统总线上，仍然可以去系统总线请求缓存行。 个性化的处理器特定的超一致性状态是单独设置的，但是通常作为一组更改为另一个一致性状态（例如，修改或无效）。