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1.发明授权Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效基于群集的多处理器系统中微处理器通信的方法和数据处理系统公开(公告)号：US07818364B2
公开(公告)日：2010-10-19
申请号：US11952479
申请日：2007-12-07
IPC分类号： G06F15/76 , G06F15/163
CPC分类号： H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译： 包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。 每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。 每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存行，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。
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2.发明授权Method, processing unit and data processing system for microprocessor communication in a multi-processor system 失效用于多处理器系统中微处理器通信的方法，处理单元和数据处理系统公开(公告)号：US07356568B2
公开(公告)日：2008-04-08
申请号：US10318514
申请日：2002-12-12
IPC分类号： G06F13/00
CPC分类号： G06F9/30101
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译： 包含在多处理器系统内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。 每个处理器在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率 无限流的加载，存储和无效命令。
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公开(公告)号：US07017031B2
公开(公告)日：2006-03-21
申请号：US10268740
申请日：2002-10-10
IPC分类号： G06F9/30
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/0811
摘要： A data processing system includes a global promotion facility containing a plurality of promotion bit fields, an interconnect, and a plurality of processing units coupled to the global promotion facility and to the interconnect. A first processing unit includes an instruction sequencing unit, an execution unit that executes an acquisition instruction to acquire a particular promotion bit field within the global promotion facility, and a promotion awareness facility. In response to the first processing unit snooping a request by a second processing unit for the particular promotion bit field, the first processing unit records an association between the second processing unit and the particular promotion bit field in the global promotion facility. After the request and release of the particular promotion bit field by the first processing unit, the first processing unit checks the promotion awareness facility for an association for the particular promotion bit and responsive to the checking, pushes the particular promotion bit field to the second processing unit utilizing an unsolicited operation on the interconnect such that no additional request by the second processing unit is required.
摘要翻译： 数据处理系统包括包含多个升级位字段的全球推广设施，互连以及耦合到全球促销设施和互连的多个处理单元。 第一处理单元包括指令排序单元，执行单元，执行获取指令以获取全球促销设施内的特定促销位字段，以及促销意识设施。 响应于第一处理单元窥探特定促销位字段的第二处理单元的请求，第一处理单元在全局推广设备中记录第二处理单元和特定促销位字段之间的关联。 在由第一处理单元请求和释放特定促销位字段之后，第一处理单元检查促销感知设施以获得针对特定促销位的关联并且响应于检查，将特定促销位字段推送到第二处理 在所述互连上使用非请求操作的单元，使得不需要所述第二处理单元的附加请求。
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4.发明授权System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture 失效系统和方法能够使稳定的存储优势与稳定的存储架构相结合公开(公告)号：US06963967B1
公开(公告)日：2005-11-08
申请号：US09588508
申请日：2000-06-06
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In response to receipt of the memory access instruction a memory access request and a barrier operation are created. The barrier operation is placed on an interconnect after the memory access request is issued to a memory system. After the barrier operation has completed, the memory access request is completed in program order. When the memory access request is a load request, the load request is speculatively issued if a barrier operation is pending. Data returned by the speculatively issued load request is only returned to a register or execution unit of the processor when an acknowledgment is received for the barrier operation.
摘要翻译： 公开了一种在数据处理系统中处理指令的方法。 包括存储器访问指令的指令序列以处理器的顺序被接收。 响应于接收到存储器访问指令，创建存储器访问请求和屏障操作。 在将存储器访问请求发布到存储器系统之后，屏障操作被放置在互连上。 屏障操作完成后，按程序顺序完成内存访问请求。 当存储器访问请求是加载请求时，如果屏障操作正在等待，则推测性地发出加载请求。 当接收到用于屏障操作的确认时，由推测发出的加载请求返回的数据仅返回到处理器的寄存器或执行单元。
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5.发明授权High performance symmetric multiprocessing systems via super-coherent data mechanisms 失效通过超相干数据机制的高性能对称多处理系统公开(公告)号：US06785774B2
公开(公告)日：2004-08-31
申请号：US09978362
申请日：2001-10-16
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that, responsive to a receipt of a first system bus response to a coherency operation, causes the requesting processor to execute operations utilizing super-coherent data. The data processing system further includes logic eventually returning to coherent operations with other processing units responsive to an occurrence of a pre-determined condition. The coherency protocol of the data processing system includes a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of the data processing system. When the cache line is in the first coherency state, subsequent requests for the cache line is issued as a Z1 read on a system bus and one of two responses are received. If the response to the Z1 read indicates that the first processor should utilize local data currently available within the cache line, the first coherency state is changed to a second coherency state that indicates to the first processor that subsequent request for the cache line should utilize the data within the local cache and not be issued to the system interconnect. Coherency state transitions to the second coherency state is completed via the coherency protocol of the data processing system. Super-coherent data is provided to the processor from the cache line of the local cache whenever the second coherency state is set for the cache line and a request is received.
摘要翻译： 一种多处理器数据处理系统，包括多个处理单元，多个高速缓存，每个高速缓存与每个处理单元中的一个相关联;以及处理逻辑，响应于对一致性操作的第一系统总线响应的接收，使得 请求处理器使用超相干数据执行操作。 数据处理系统还包括逻辑，其最终返回到响应于预定条件的发生的其他处理单元的相干操作。 数据处理系统的一致性协议包括第一相关性状态，其指示在数据处理系统的系统总线上已经窥探第二处理器的第二高速缓存的共享高速缓存行内的数据的修改。 当高速缓存行处于第一相关性状态时，在系统总线上作为Z1读取发出对高速缓存行的后续请求，并且接收到两个响应中的一个。 如果对Z1读取的响应指示第一处理器应利用高速缓存行内当前可用的本地数据，则将第一相关性状态改变为第二相关性状态，其向第一处理器指示对高速缓存行的后续请求应当利用 本地缓存内的数据，不发给系统互连。 通过数据处理系统的一致性协议完成一致性状态转换到第二相关性状态。 每当为高速缓存行设置第二相关性状态并接收到请求时，将超相干数据从本地高速缓存行提供给处理器。
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6.发明授权System and method for asynchronously overlapping storage barrier operations with old and new storage operations 有权使用旧的和新的存储操作异步重叠存储屏障操作的系统和方法公开(公告)号：US06609192B1
公开(公告)日：2003-08-19
申请号：US09588607
申请日：2000-06-06
IPC分类号： G06F9312
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3842
摘要： Disclosed is a multiprocessor data processing system that executes loads transactions out of order with respect to a barrier operation. The data processing system includes a memory and a plurality of processors coupled to an interconnect. At least one of the processors includes an instruction sequencing unit for fetching an instruction sequence in program order for execution. The instruction sequence includes a first and a second load instruction and a barrier instruction, which is between the first and second load instructions in the instruction sequence. Also included in the processor is a load/store unit (LSU), which has a load request queue (LRQ) that temporarily buffers load requests associated with the first and second load instructions. The LRQ is coupled to a load request arbitration unit, which selects an order of issuing the load requests from the LRQ. Then a controller issues a load request associated with the second load instruction to memory before completion of a barrier operation associated with the barrier instruction. Alternatively, load requests are issued out-of-order with respect to the program order before or after the barrier instruction. The load request arbitration unit selects the request associated with the second load instruction before a request associated with the first load instruction, and the controller issues the request associated with the second load instruction before the request associated with the first load instruction and before issuing the barrier operation.
摘要翻译： 公开了一种多处理器数据处理系统，其针对屏障操作执行无序的负载事务。 数据处理系统包括存储器和耦合到互连的多个处理器。 至少一个处理器包括用于以程序顺序取出指令序列以执行的指令排序单元。 指令序列包括在指令序列中的第一和第二加载指令之间的第一和第二加载指令和障碍指令。 还包括在处理器中的是装载/存储单元（LSU），其具有临时缓冲与第一和第二加载指令相关联的加载请求的加载请求队列（LRQ）。 LRQ耦合到负载请求仲裁单元，该单元从LRQ中选择发出负载请求的顺序。 然后，在与障碍指令相关联的屏障操作完成之前，控制器向存储器发出与第二加载指令相关联的加载请求。 或者，负载请求在屏障指令之前或之后相对于程序顺序发出无序。 负载请求仲裁单元在与第一加载指令相关联的请求之前选择与第二加载指令相关联的请求，并且控制器在与第一加载指令相关联的请求之前发布与第二加载指令相关联的请求，并且在发布屏障之前 操作。
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7.发明授权Method and apparatus for monitoring internal bus signals by using a reduced image of the internal bus 失效通过使用内部总线的缩小图像监视内部总线信号的方法和装置公开(公告)号：US06292908B1
公开(公告)日：2001-09-18
申请号：US09175391
申请日：1998-10-19
IPC分类号： G06F1130
CPC分类号： G06F11/364 , G06F11/349
摘要： An apparatus and method for monitoring an internal communication path, i.e. an internal bus, of an integrated circuit is described. The internal bus operates at a particular frequency, fb. An image of the internal bus is produced, operating at a lower frequency of operations, fo, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be “out-of-phase” with respect to one another. A buffer/align unit processes the signals in order to produce a time delayed version of the signals. The buffer/aliqn unit is used to bring each of the monitored signals back in phase relative to one another. Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, fo. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, fo.
摘要翻译： 描述了用于监视集成电路的内部通信路径即内部总线的装置和方法。 内部总线以特定频率fb运行。 生产内部总线的图像，操作频率较低，更适合于测试设备的监控。 使用驱动器/接收器电路从信号接收和驱动到总线。 信号可以是仅输入信号，仅输出信号或双向信号。 要监视的信号被点击在驱动器/接收器电路中。 根据驱动器/接收器逻辑中的信号抽头的布置，信号可能相对于彼此“异相”。 缓冲器/对准单元处理信号以产生信号的时间延迟版本。 缓冲器/ aliqn单元用于使每个被监控的信号相对于彼此反相。 编码电路以以更低的操作频率fo产生总线的图像的方式对总线的时间延迟版本进行编码。 编码电路在编码窗口中考虑监视信号的值，并且以较低的操作频率fo产生每个信号的编码值。
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公开(公告)号：US06175930B1
公开(公告)日：2001-01-16
申请号：US09024586
申请日：1998-02-17
IPC分类号： H02H305
CPC分类号： G06F12/0831
摘要： A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation—one which might affect the storage hierarchy as perceived by other devices within the system—is posted in the snoop queue of a remote snooping device. The flag remains set and is reset only when a synchronization instruction (such as the “sync” instruction supported by the PowerPC™ family of devices) is received from a local processor. The state of the flag thus provides historical information regarding architected operations which may be pending in other devices within the system after being snooped from the system bus. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered and additional system bus cycles made available for other purposes. When a local processor issues a synchronization instruction to the device managing the architected logic queue, the instruction is generally accepted when the architected logic queue is empty. Otherwise the architected operation is retried back to the local processor until the architected logic queue becomes empty. If the flag is set when the synchronization instruction is accepted from the local processor, it is presented on the system bus. If the flag is not set when the synchronization instruction is received from the local processor, the synchronization operation is unnecessary and is not presented on the system bus.
摘要翻译： 与多处理器系统中的存储器相干设备的架构化逻辑队列相关联的寄存器包含标志集，每当可以影响系统内其他设备感知到的存储层次结构的操作（一个可能影响系统中的其他设备的架构操作）被发布在 一个远程监听设备。 该标志保持置位，并且仅当从本地处理器接收到同步指令（例如由PowerPC TM系列器件支持的“sync”指令）时才会复位该标志。 因此，标志的状态提供关于在从系统总线窥探之后可能在系统内的其他设备中挂起的架构操作的历史信息。 该历史信息用于确定是否应在系统总线上呈现同步操作，从而允许滤除不必要的同步操作，并为其他目的提供额外的系统总线周期。 当本地处理器向管理架构的逻辑队列的设备发出同步指令时，当架构的逻辑队列为空时，通常会接受该指令。 否则，架构操作将重新回到本地处理器，直到架构化的逻辑队列变为空。 如果在本地处理器接受同步指令时设置了标志，则会将其显示在系统总线上。 如果当从本地处理器接收到同步指令时未设置标志，则不需要同步操作，并且不会在系统总线上呈现同步操作。
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9.发明授权Method and apparatus for monitoring 60x bus signals at a reduced frequency 失效用于以降低的频率监视60x总线信号的方法和装置
公开(公告)号：US6092132A
公开(公告)日：2000-07-18
申请号：US175612
申请日：1998-10-19
CPC分类号： G06F13/4213
摘要： An apparatus and method for monitoring a PowerPC 60x bus within an integrated circuit is described. The 60x bus operates at a particular frequency, f.sub.b. An image of the 60x bus is produced, operating at a lower frequency of operations, f.sub.o, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Masking circuitry within the driver/receiver circuitry masks bi-directional signals, such as ARTRY.sub.-- and SHD.sub.--, during the pre-charge cycles, when these bi-directional signals are in an unpredictable state. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be "out-of-phase" with respect to one another. A buffer/align unit is used to bring each of the monitored signals back in phase relative to one another. Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, f.sub.o. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, f.sub.o.
摘要翻译： 描述了用于监视集成电路内的PowerPC 60x总线的装置和方法。 60x总线以特定频率fb运行。 生产60x总线的图像，操作频率较低，更适合于测试设备的监控。 使用驱动器/接收器电路从信号接收和驱动到总线。 信号可以是仅输入信号，仅输出信号或双向信号。 要监视的信号被点击在驱动器/接收器电路中。 当这些双向信号处于不可预测状态时，驱动器/接收器电路内的屏蔽电路在预充电周期期间屏蔽双向信号，例如ARTRY-和SHD-。 根据驱动器/接收器逻辑中的信号抽头的布置，信号可能相对于彼此“异相”。 使用缓冲器/对准单元使每个被监视的信号相对于彼此同相。 编码电路以以更低的操作频率fo产生总线的图像的方式对总线的时间延迟版本进行编码。 编码电路在编码窗口中考虑监视信号的值，并且以较低的操作频率fo产生每个信号的编码值。
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10.发明授权Apparatus and method for separately layering cache and architectural specific functions in different operational controllers 失效用于在不同操作控制器中单独分层缓存和架构特定功能的装置和方法
公开(公告)号：US6061762A
公开(公告)日：2000-05-09
申请号：US839442
申请日：1997-04-14
CPC分类号： G06F12/0802
摘要： Cache and architectural specific functions are layered within a controller, simplifying design requirements. Faster performance may be achieved and individual segments of the overall design may be individually tested and formally verified. Transition between memory consistency models is also facilitated. Different segments of the overall design may be implemented in distinct integrated circuits, allowing less expensive processes to be employed where suitable.
摘要翻译： 缓存和架构特定功能在控制器内分层，简化了设计要求。 可以实现更快的性能，并且可以单独测试和正式验证整体设计的各个部分。 内存一致性模型之间的转换也是有利的。 总体设计的不同部分可以在不同的集成电路中实现，从而允许在合适的情况下采用较便宜的工艺。
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