公开(公告)号：US06766501B1

公开(公告)日：2004-07-20

申请号：US10217490

申请日：2002-08-12

Applicant: Suryanarayana Duggirala ,  Rohit Kapur ,  Thomas W. Williams

Inventor： Suryanarayana Duggirala ,  Rohit Kapur ,  Thomas W. Williams

IPC: G06F1750

CPC classification number: G01R31/318594 ,  G01R31/318536 ,  G01R31/318583

Abstract: A process and system for placement planning for test mode circuitry of an integrated circuit design. The novel method includes the steps of partitioning a scan chain of a netlist into sets of re-orderable scan cells. The netlist is passed to layout processes and therein the scan cells of the scan chain are re-ordered based on the sets. According to one embodiment of the present invention, the scan-chain is partitioned into a number of different sets based the respective clock domains, edge sensitivity types, skew tolerance levels, surrounding cone logic, reconfigurability and simultaneous output switching requirements of the scan cells. Data representative of the resulting sets are then provided to the place-and-route processes to be used as re-ordering limitations. Particularly, the re-ordering limitations restrict the rearrangement of scan cells among different sets. The placement and routing processes, however, are not restricted from rearranging the order of scan cells within the same set. The present invention thereby allows a better designed integrated circuit to be designed and fabricated.

Abstract translation: 用于集成电路设计的测试模式电路的布局规划的过程和系统。 该新颖方法包括以下步骤：将网表的扫描链分成可重排序扫描单元的集合。 网表被传递到布局处理，其中扫描链的扫描单元基于这些集合被重新排序。 根据本发明的一个实施例，扫描链根据扫描单元的相应时钟域，边缘灵敏度类型，偏斜容差水平，周围锥形逻辑，可重构性和同时输出切换要求被划分成多个不同的集合。 然后将代表结果集的数据提供给用于重新排序限制的地点和路由过程。 特别地，重新排序限制限制了不同组之间的扫描单元的重排。 然而，放置和布线过程不限于重新排列同一集合内的扫描单元的顺序。 因此，本发明允许设计和制造更好设计的集成电路。

公开(公告)号：US06453437B1

公开(公告)日：2002-09-17

申请号：US09348712

申请日：1999-07-01

Applicant: Rohit Kapur ,  Thomas W. Williams ,  John Waicukauski ,  Peter Wohl

Inventor： Rohit Kapur ,  Thomas W. Williams ,  John Waicukauski ,  Peter Wohl

IPC: G01R3128

CPC classification number: G06F11/263 ,  G01R31/318342

Abstract: A method for generating a test pattern for use in testing an integrated circuit device. The computer implemented steps of receiving and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the netlist simulation, a set of circuit paths for each fault of the plurality of faults within the netlist specification is determined. From this set of paths, respective longest paths for each fault is determined. Using an ATPG (automatic test pattern generation) process, a test vector is determined for the first fault. Transition fault simulation is then performed on the first fault by applying the test vector to a first path through the first fault, wherein the first path is the longest path traversing through the first fault as determined by the ATPG process. Responsive to the transition fault simulation, a second fault that is fortuitously detected by the test vector as applied to a second path traversing through the second fault is identified. The test vector is credited with detecting the first fault, and, provided the second path is the longest path that traverses through the second fault, the test vector is credited with detecting the second fault. If the second path is not the longest path, a test vector is generated in a subsequent iteration of the method. In so doing, the method ensures transition faults are detected along long paths as opposed to short paths, thereby improving test quality.

Abstract translation: 一种用于产生用于测试集成电路器件的测试图案的方法。 计算机实现在计算机存储器单元中接收和存储网表规范的步骤，以及使用计算机实现的合成系统来模拟网表。 使用网表模拟，确定网表规范内的多个故障的每个故障的一组电路路径。 从这组路径中，确定每个故障的相应最长路径。 使用ATPG（自动测试模式生成）过程，确定第一个故障的测试向量。 然后通过将测试向量应用于通过第一故障的第一路径，对第一故障进行过渡故障模拟，其中第一路径是通过ATPG过程确定的穿过第一故障的最长路径。 响应于过渡故障模拟，识别出应用于穿过第二故障的第二路径的由测试矢量偶然检测到的第二故障。 测试矢量被检测到第一个故障，并且如果第二个路径是穿过第二个故障的最长路径，则测试向量被检测到第二个故障。 如果第二条路径不是最长路径，则在该方法的后续迭代中生成测试向量。 在这样做的过程中，该方法可以确保沿短路径沿长路径检测到过渡故障，从而提高测试质量。

公开(公告)号：US5691990A

公开(公告)日：1997-11-25

申请号：US759286

申请日：1996-12-02

Applicant: Rohit Kapur ,  Thomas J. Snethen ,  Kamran K. Zarrineh

Inventor： Rohit Kapur ,  Thomas J. Snethen ,  Kamran K. Zarrineh

IPC: G01R31/3185 ,  G06F11/00

CPC classification number: G01R31/318586

Abstract: An efficient method of selecting flip-flops to be made scannable in a digital integrated circuit design for purposes of improving testability without incurring the overhead of full-scan, comprising the steps of (a) partitioning the faults in the circuit into a first fault type and a second fault type, (b) selecting a static characterization algorithm for characterizing the first and second fault types, (c) determining the relationship between attainable fault coverage and the characterized values for the first and second fault types, (d) characterizing the first and second fault types for each candidate flip-flop for scan in the digital integrated circuit with the static characterization algorithm, (e) determining the first and second fault types that are the closest together in value, (f) selecting the flip-flop associated with the first and second fault types determined in step (e), (g) forming a shift register with flip-flop selected in step (f), (h) repeating steps (d)-(g) until the attainable fault coverage determined in step (c) is attained, and (i) generating test data for the network with the shift register configured in step (h).

Abstract translation: 为了提高可测试性而不引起全扫描的开销，选择在数字集成电路设计中可扫描的触发器的有效方法包括以下步骤：（a）将电路中的故障划分为第一故障类型 和第二故障类型，（b）选择表征第一和第二故障类型的静态表征算法，（c）确定可达到的故障覆盖与第一和第二故障类型的特征值之间的关系，（d） 使用静态表征算法在数字集成电路中扫描每个候选触发器的第一和第二故障类型，（e）确定在值中最接近的第一和第二故障类型，（f）选择触发器 与在步骤（e）中确定的第一和第二故障类型相关联，（g）在步骤（f）中形成具有触发器的移位寄存器，（h）重复步骤（d） - （g） 获得在步骤（c）中确定的可达到的故障覆盖范围，并且（i）利用在步骤（h）中配置的移位寄存器生成网络的测试数据。

公开(公告)号：US08660818B2

公开(公告)日：2014-02-25

申请号：US12854120

申请日：2010-08-10

Applicant: Rohit Kapur ,  Mallika Kapur ,  Maya Kapur

Inventor： Rohit Kapur ,  Mallika Kapur ,  Maya Kapur

IPC: G06F11/07

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method of performing systemic diagnostics for a wafer includes selecting a design for manufacturability (DFM) rule for analysis. For each IC chip on the wafer, two sets of IC features adjacent the rule can be extracted based on the chip's layout design. Upconverted diagnostics can be run to generate computed numbers associated with combination categories for each set. Zonal analysis can be run on the two sets using the computed numbers to derive metrics for the two sets. A report can be generated based on the zonal analysis.

Abstract translation: 为晶片执行系统诊断的方法包括选择用于分析的可制造性（DFM）规则的设计。 对于晶片上的每个IC芯片，可以基于芯片的布局设计提取与规则相邻的两组IC特征。 可以运行上转换的诊断程序，以生成与每个组合的组合类别相关联的计算数字。 可以使用计算的数字在两组上运行区域分析，以得出两组的度量。 可以根据区域分析生成报告。

公开(公告)号：US20090313514A1

公开(公告)日：2009-12-17

申请号：US12546595

申请日：2009-08-24

Applicant: Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

Inventor： Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

IPC: G01R31/28

CPC classification number: G01R31/318572 ,  G01R31/318536

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

公开(公告)号：US20090271673A1

公开(公告)日：2009-10-29

申请号：US12500296

申请日：2009-07-09

Applicant: Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic J. Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

Inventor： Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic J. Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318572 ,  G01R31/318536

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract translation: 提供了低开销动态可重配置的共享扫描测试架构。 该测试架构有利地允许在每次移动的扫描操作期间改变扫描输入。 重新配置扫描输入到每个移位周期扫描链映射的灵活性可以有利地减少测试数据量和测试应用时间。

公开(公告)号：US20090235133A1

公开(公告)日：2009-09-17

申请号：US12469820

申请日：2009-05-21

Applicant: Rohit Kapur ,  Tom W. Williams ,  Cyrus Hay

Inventor： Rohit Kapur ,  Tom W. Williams ,  Cyrus Hay

IPC: G01R31/28

CPC classification number: G01R31/31725

Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

Abstract translation: 一种生成用于检测集成电路（IC）中的过渡故障的测试模式的系统。 在操作期间，系统为IC中的每个网络收到松弛时间。 请注意，网络的松弛时间是给定网络在违反时序约束之前可以容忍的最小延迟时间。 对于IC中的每个可能的过渡故障，系统使用IC中的网络的松弛时间来产生测试模式，该测试模式通过产生沿着最长路径传播到转换故障的转变来暴露过渡故障。

公开(公告)号：US07546500B2

公开(公告)日：2009-06-09

申请号：US11366679

申请日：2006-03-02

Applicant: Rohit Kapur ,  Tom W. Williams ,  Cyrus Hay

Inventor： Rohit Kapur ,  Tom W. Williams ,  Cyrus Hay

IPC: G01R31/28

CPC classification number: G01R31/31725

Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

Abstract translation: 一种生成用于检测集成电路（IC）中的过渡故障的测试模式的系统。 在操作期间，系统为IC中的每个网络收到松弛时间。 请注意，网络的松弛时间是给定网络在违反时序约束之前可以容忍的最小延迟时间。 对于IC中的每个可能的过渡故障，系统使用IC中的网络的松弛时间来产生测试模式，该测试模式通过产生沿着最长路径传播到转换故障的转变来暴露过渡故障。

公开(公告)号：US20080256497A1

公开(公告)日：2008-10-16

申请号：US11807119

申请日：2007-05-25

Applicant: Peter Wohl ,  John A. Waicukauski ,  Sanjay Ramnath ,  Rohit Kapur ,  Thomas W. Williams

Inventor： Peter Wohl ,  John A. Waicukauski ,  Sanjay Ramnath ,  Rohit Kapur ,  Thomas W. Williams

IPC: H03K19/173 ,  G06F17/50

CPC classification number: H03M7/30 ,  G06F17/505 ,  G06F2217/14

Abstract: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.

Abstract translation: 基于扫描的电路包括通过多个观察逻辑实现的选择器。 每个观察逻辑耦合到扫描链以接收要提供给组合式压缩机的数据。 每个观察逻辑还耦合到组合压缩机的相应组输入线中的单个输入线，以选择性地从耦合的扫描链提供数据。 每个观察逻辑可以耦合到相应组中的附加输入线（如果存在）。 在（a）透明模式中，选择器可以在每个移位的基础上操作，其中数据被提供给所有输入线，并且（b）几个直接模式，其中来自仅一个扫描链的数据仅在每个压缩器输出处被提供而不重叠。

公开(公告)号：US20070206354A1

公开(公告)日：2007-09-06

申请号：US11366679

申请日：2006-03-02

Applicant: Rohit Kapur ,  Tom Williams ,  Cyrus Hay

Inventor： Rohit Kapur ,  Tom Williams ,  Cyrus Hay

IPC: H05K7/20

CPC classification number: G01R31/31725

Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

Abstract translation: 一种生成用于检测集成电路（IC）中的过渡故障的测试模式的系统。 在操作期间，系统为IC中的每个网络收到松弛时间。 请注意，网络的松弛时间是给定网络在违反时序约束之前可以容忍的最小延迟时间。 对于IC中的每个可能的过渡故障，系统使用IC中的网络的松弛时间来产生测试模式，该测试模式通过产生沿着最长路径传播到转换故障的转变来暴露过渡故障。