公开(公告)号：US08988160B2

公开(公告)日：2015-03-24

申请号：US13004609

申请日：2011-01-11

申请人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

发明人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

IPC分类号： H03H2/00 ,  H03H7/38 ,  H04B3/02

CPC分类号： H04B3/02

摘要： A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed.The data transmission system transmitting data from an output buffer to the input buffer through a trace is provided with first RC parallel circuits connected in series to the trace on a first Printed Circuit Board (PCB) on which the output buffer is mounted, and second RC parallel circuits connected in series to the trace on a second Printed Circuit Board (PCB) on which the input buffer is mounted, and which can be connected and separated to and from the first Printed Circuit Board (PCB).

摘要翻译： 提供了一种数据传输系统，其中即使输入缓冲器的负载电容改变，也可以同时执行抑制转换速率的降级和抑制振铃的两者。 通过轨迹将数据从输出缓冲器传输到输入缓冲器的数据传输系统提供有与其上安装有输出缓冲器的第一印刷电路板（PCB）上的迹线串联连接的第一RC并联电路，以及第二RC 并联电路与安装有输入缓冲器的第二印刷电路板（PCB）上的迹线串联连接，并且可以与第一个印刷电路板（PCB）连接和分离。

公开(公告)号：US08581622B1

公开(公告)日：2013-11-12

申请号：US13512465

申请日：2012-05-16

申请人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

发明人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

IPC分类号： H03K17/16

CPC分类号： G11C7/10 ,  G11C7/1057 ,  G11C7/1084

摘要： To suppress power consumption and enhance signal quality as compared with the case where first and second semiconductor elements are terminated only by on-chip input termination resistor circuits. A first semiconductor element with a switching function and a second semiconductor element with a switching function are connected to each other with a substrate interconnection, and a resistor element is connected in parallel with the substrate interconnection. The resistor element is placed at an arbitrary position or a branch point on the signal interconnection.

摘要翻译： 与第一和第二半导体元件仅由片上输入终端电阻电路端接的情况相比，抑制功耗和提高信号质量。 具有开关功能的第一半导体元件和具有开关功能的第二半导体元件通过衬底互连彼此连接，并且电阻元件与衬底互连并联连接。 电阻元件放置在信号互连的任意位置或分支点处。

公开(公告)号：US20120302075A1

公开(公告)日：2012-11-29

申请号：US13481013

申请日：2012-05-25

申请人： Satoshi MURAOKA ,  Masayoshi YAGYU

发明人： Satoshi MURAOKA ,  Masayoshi YAGYU

IPC分类号： H05K1/11 ,  H01R12/00

CPC分类号： H05K1/0251 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/10295 ,  H05K2203/0207

摘要： The present invention maintains plugging-unplugging durability of connector pins for connecting to a signal wiring board, as well as reduces a stub length of a through hole connecting to a signal wiring. In the signal wiring board according to the present invention, a through hole connecting to the inner-layer signal wiring is formed to be shorter than the other through holes. A through hole in which a connector pin connecting to the inner-layer signal wiring is inserted is formed to have a length corresponding to a depth of the inner-layer signal wiring.

摘要翻译： 本发明保持用于连接到信号线路板的连接器针的插拔耐久性，并且减少连接到信号线的通孔的短截线长度。 在根据本发明的信号线路板中，连接到内层信号线的通孔形成为比其他通孔短。 其中插入连接到内层信号布线的连接器针的通孔形成为具有与内层信号布线的深度对应的长度。

公开(公告)号：US20120112849A1

公开(公告)日：2012-05-10

申请号：US13004609

申请日：2011-01-11

申请人： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Satoshi MURAOKA

发明人： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Satoshi MURAOKA

IPC分类号： H03H2/00 ,  H03H7/38

CPC分类号： H04B3/02

摘要： A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed.The data transmission system transmitting data from an output buffer to the input buffer through a trace is provided with first RC parallel circuits connected in series to the trace on a first Printed Circuit Board (PCB) on which the output buffer is mounted, and second RC parallel circuits connected in series to the trace on a second Printed Circuit Board (PCB) on which the input buffer is mounted, and which can be connected and separated to and from the first Printed Circuit Board (PCB).

摘要翻译： 提供了一种数据传输系统，其中即使输入缓冲器的负载电容改变，也可以同时执行抑制转换速率的降级和抑制振铃的两者。 通过轨迹将数据从输出缓冲器传输到输入缓冲器的数据传输系统提供有与其上安装有输出缓冲器的第一印刷电路板（PCB）上的迹线串联连接的第一RC并联电路，以及第二RC 并联电路与安装有输入缓冲器的第二印刷电路板（PCB）上的迹线串联连接，并且可以与第一个印刷电路板（PCB）连接和分离。

公开(公告)号：US5844762A

公开(公告)日：1998-12-01

申请号：US762691

申请日：1996-12-12

申请人： Hideho Yamamura ,  Masakazu Yamamoto ,  Naoki Maru ,  Satoshi Muraoka

发明人： Hideho Yamamura ,  Masakazu Yamamoto ,  Naoki Maru ,  Satoshi Muraoka

IPC分类号： H03H7/01 ,  G06F1/26 ,  H03H2/00 ,  H05K1/02 ,  H05K3/46 ,  H05K9/00 ,  H02H3/22

CPC分类号： H05K1/0234 ,  H05K1/0231 ,  H05K2201/09309 ,  H05K2201/10022 ,  H05K2201/10522 ,  H05K2201/10689

摘要： An electronic circuit device having a power wiring resonance inhibition function includes a plurality of electronic circuit elements, and a wiring board having the electronic circuit elements disposed thereon. The wiring board includes a plurality of planar power supply wires for supplying power to the electronic circuit elements. The planar power wires include a pair of planar power supply wires for supplying power to the electronic circuit elements at a predetermined voltage. The electronic circuit device also includes a plurality of damping elements disposed at a plurality of positions on the wiring board. The damping elements are connected between the pair of planar power supply wires at a plurality of positions on the pair of planar power supply wires. The damping elements reduce power supply system impedance and inhibit power wiring system resonance, thereby reducing supply voltage fluctuation caused by the power wiring system resonance and noise caused by the supply voltage fluctuation.

摘要翻译： 具有电力线共振抑制功能的电子电路装置包括多个电子电路元件，以及配置有电子电路元件的布线基板。 布线板包括用于向电子电路元件供电的多个平面电源线。 平面电力线包括用于以预定电压向电子电路元件供电的一对平面电源线。 电子电路装置还包括布置在布线板上的多个位置处的多个阻尼元件。 阻尼元件在一对平面电源线的多个位置处连接在一对平面电源线之间。 阻尼元件降低了电源系统的阻抗，并阻止了电源线路系统的共振，从而减少了由电源线路系统引起的电源电压波动和由电源电压波动引起的噪声。