公开(公告)号：US4459606A

公开(公告)日：1984-07-10

申请号：US644296

申请日：1975-12-24

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L29/73 ,  H01L27/04 ,  H03K19/091

CPC分类号： H01L27/0214

摘要： The integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on the N type semiconductor substrate, a first N type region extending through the P type semiconductor layer to reach the N type semiconductor substrate, a P type region formed in the first N type region and having a periphery along the outer periphery of the first N type region and a second N type region formed in the P type semiconductor layer. The integrated injection logic semiconductor device is constituted by a PNP lateral transistor utilizing the P type region, the first N type region and the P type semiconductor layer as the emitter, base and collector electrodes respectively, and a NPN vertical transistor utilizing the N type semiconductor substrate, P type semiconductor layer and the second N type region as the emitter, base and collector electrodes, respectively.

摘要翻译： 集成注入逻辑半导体器件包括N型半导体衬底，层叠在N型半导体衬底上的P型半导体层，延伸穿过P型半导体层到达N型半导体衬底的第一N型区域，P型区域 形成在第一N型区域中，并且沿着第一N型区域的外周具有周边，以及形成在P型半导体层中的第二N型区域。 集成注入逻辑半导体器件分别由利用P型区域，第一N型区域和P型半导体层作为发射极，基极和集电极的PNP横向晶体管构成，以及利用N型半导体的NPN垂直晶体管 基板，P型半导体层和第二N型区域分别作为发射极，基极和集电极。

公开(公告)号：US4058419A

公开(公告)日：1977-11-15

申请号：US644294

申请日：1975-12-24

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L21/033 ,  H01L21/8226 ,  H01L27/02 ,  H01L21/22 ,  H01L21/76 ,  H01L27/04

CPC分类号： H01L21/8226 ,  H01L21/033 ,  H01L27/0233

摘要： A P type semiconductor layer is formed on an N type semiconductor layer by vapour epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.

摘要翻译： 通过蒸气外延生长技术在N型半导体层上形成P型半导体层，在P型半导体层上形成绝缘膜，通过绝缘膜设置栅格状的第一开口。 然后，磷通过栅格形状开口扩散到P型半导体层中，以形成延伸穿过半导体层的第一N型区域到达N型半导体层。 然后，通过由栅格形状的第一开口分隔并被其包围的绝缘膜的各个部分形成第二开口，并且硼通过第一和第二开口扩散，以形成网格形状的第一N型区域中的第一和第二P型区域， P型半导体层。 最后，通过绝缘膜的各部分形成第三开口，并且磷通过第三开口扩散到P型半导体层中，以形成第二N型区域，从而形成包括横向PNP晶体管和垂直NPN的集成注入逻辑半导体器件 晶体管。

公开(公告)号：US08078690B2

公开(公告)日：2011-12-13

申请号：US12071897

申请日：2008-02-27

申请人： Norio Shimozono ,  Shintaro Ito

发明人： Norio Shimozono ,  Shintaro Ito

IPC分类号： G06F15/16

CPC分类号： G06F17/30067 ,  G06F17/3007 ,  G06F17/30079 ,  H04L49/253 ,  H04L49/30 ,  H04L49/50 ,  H04L49/501 ,  H04L49/70 ,  H04Q1/56

摘要： A switch unit, which is connected to one or more computers and one or more storage systems, comprises an update function for updating transfer management information (a routing table, for example). The storage system has a function for adding a virtual port to a physical port. The storage system migrates the virtual port addition destination from a first physical port to a second physical port and transmits a request of a predetermined type which includes identification information on the virtual port of the migration target to the switch unit. The transfer management information is updated by the update function of the switch unit so that the transfer destination which corresponds with the migration target virtual port is the switch port connected to the second physical port.

摘要翻译： 连接到一个或多个计算机和一个或多个存储系统的开关单元包括用于更新传送管理信息（例如路由表）的更新功能。 存储系统具有将虚拟端口添加到物理端口的功能。 存储系统将虚拟端口添加目的地从第一物理端口迁移到第二物理端口，并将包括迁移目标的虚拟端口上的标识信息的预定类型的请求发送到交换单元。 通过切换单元的更新功能来更新传送管理信息，使得与移动对象虚拟端口对应的传送目的地是连接到第二物理端口的交换端口。

公开(公告)号：US08037245B2

公开(公告)日：2011-10-11

申请号：US12026858

申请日：2008-02-06

申请人： Manabu Kitamura ,  Junji Ogawa ,  Shunji Kawamura ,  Takao Sato ,  Naoto Matsunami ,  Shintaro Ito ,  Tomohiro Yoshihara ,  Takuji Ogawa

发明人： Manabu Kitamura ,  Junji Ogawa ,  Shunji Kawamura ,  Takao Sato ,  Naoto Matsunami ,  Shintaro Ito ,  Tomohiro Yoshihara ,  Takuji Ogawa

IPC分类号： G06F12/16 ,  H03M13/11

CPC分类号： G06F11/1076 ,  G06F2211/1014

摘要： One code (a compressed redundant code) is created based on a plurality of first redundant codes, each created on the basis of a plurality of data units, and this compressed redundant code is written to a nonvolatile storage area. This compressed redundant code is used to restore either a data element constituting a multiple-failure data, or a first redundant code corresponding to the multiple-failure data, which is stored in an unreadable sub-storage area of a partially failed storage device, and to restore the data element constituting the multiple-failure data which is stored in a sub-storage area of a completely failed storage device, based on the restored either data element or first redundant code, and either another data element constituting the multiple-failure data or the first redundant code corresponding to the multiple-failure data.

摘要翻译： 基于多个基于多个数据单元创建的多个第一冗余代码来创建一个代码（压缩冗余代码），并将该压缩的冗余代码写入非易失性存储区域。 该压缩冗余代码用于恢复存储在部分故障存储设备的不可读子存储区域中的构成多故障数据的数据元素或对应于多故障数据的第一冗余代码，以及 基于恢复的数据元素或第一冗余代码，恢复存储在完全失败的存储设备的子存储区域中的构成多故障数据的数据元素，以及构成多故障数据的另一数据元素 或对应于多故障数据的第一冗余码。

公开(公告)号：US4637125A

公开(公告)日：1987-01-20

申请号：US847150

申请日：1986-04-03

申请人： Hiroshi Iwasaki ,  Shintaro Ito

发明人： Hiroshi Iwasaki ,  Shintaro Ito

IPC分类号： H01L21/8249 ,  H01L21/38

CPC分类号： H01L21/8249

摘要： A semiconductor integrated device (CBi-CMOS) is disclosed wherein both CMOS transistors and a vertical npn and pnp transistor are formed in a single semiconductor substrate and a latch up phenomenon in the CMOS is prevented. A method of manufacturing the CBi-CMOS is also disclosed. In the CBi-CMOS, four elements, that is, an n-MOSFET, a p-MOSFET and npn and pnp vertical transistors are formed in an n-type epitaxial silicon layer formed on a p-type silicon substrate. The n-MOSFET is formed in a p-well which has a p.sup.+ -type buried region. In the element region of the p-MOSFET, an n.sup.+ -type buried region is also formed. In the element regions of the npn and pnp vertical transistors, a first p.sup.+ -type isolation diffusion region is selectively formed. An n.sup.+ -type buried region is selectively formed in both of these element region of the npn and pnp vertical transistors. In the element region of the npn transistor, the vertical npn transistor is formed using the n-type region surrounded by the first p.sup.+ -type isolation diffusion region as a collector. In the element region of the pnp transistor, a p.sup.+ -type buried region is formed on the n.sup.+ -type buried region, and the vertical pnp transistor is formed using the p.sup.+ -type buried region as a collector. In this case, a second p.sup.+ -type isolation diffusion region is formed to isolate an n-type base region of the vertical pnp transistor.

摘要翻译： 公开了一种半导体集成器件（CBi-CMOS），其中在单个半导体衬底中形成CMOS晶体管和垂直npn和pnp晶体管，并且防止了CMOS中的闭锁现象。 还公开了制造CBi-CMOS的方法。 在CBi-CMOS中，在p型硅衬底上形成的n型外延硅层中形成四个元件，即n-MOSFET，p-MOSFET和npn和pnp垂直晶体管。 n-MOSFET形成在具有p +型掩埋区的p阱中。 在p-MOSFET的元件区域中，也形成n +型掩埋区域。 在npn和pnp垂直晶体管的元件区域中，选择性地形成第一p +型隔离扩散区域。 在npn和pnp垂直晶体管的这些元件区域中选择性地形成n +型掩埋区域。 在npn晶体管的元件区域中，使用由第一p +型隔离扩散区域包围的n型区域作为集电极形成垂直npn晶体管。 在pnp晶体管的元件区域中，在n +型掩埋区域上形成p +型掩埋区域，使用p +型掩埋区域作为集电体形成垂直pnp晶体管。 在这种情况下，形成第二p +型隔离扩散区，以隔离垂直pnp晶体管的n型基极区。