公开(公告)号：US4466180A

公开(公告)日：1984-08-21

申请号：US277464

申请日：1981-06-25

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L27/04 ,  H01L21/263 ,  H01L21/31 ,  H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L29/735 ,  H01L21/22

CPC classification number: H01L21/2633 ,  H01L21/76237 ,  H01L29/735

Abstract: The invention is a punch through voltage regulator having an active region formed on a substrate by any one of four different methods. Each method includes recessing the substrate substantially along the periphery of the regulator active region, selectively doping the regulator active region through portions of the recess, filling the recesses with substrate oxide to isolate the active region from the substrate and forming conductors to selectively doped portions of the active region to serve as electrode connections. For P doped substrates N type doping is introduced via the recesses and in a second method the recesses are deepened and P type doping is introduced into the substrate to change the doping in the active region. For N doped substrates P type doping is introduced via the recesses and when the recesses are deepened in the fourth method, N type doping is introduced into the substrate to change the doping of the active portion.

Abstract translation: 本发明是通过四种不同方法中的任何一种形成在衬底上的有源区的穿孔式电压调节器。 每种方法包括基本上沿着调节器有源区域的周边凹陷衬底，通过凹部的一部分选择性地掺杂调节器有源区，用衬底氧化物填充凹陷，以将有源区与衬底隔离，并形成导体以选择性掺杂部分 有源区域用作电极连接。 对于P掺杂衬底，通过凹槽引入N型掺杂，并且在第二种方法中，凹陷被加深，并且P型掺杂被引入到衬底中以改变有源区域中的掺杂。 对于N掺杂衬底，通过凹槽引入P型掺杂，并且当在第四种方法中加深凹槽时，将N型掺杂引入衬底中以改变有源部分的掺杂。

公开(公告)号：US4435899A

公开(公告)日：1984-03-13

申请号：US450310

申请日：1982-12-16

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/762 ,  H01L29/10 ,  H01L29/735 ,  H01L21/302

CPC classification number: H01L29/1008 ,  H01L21/265 ,  H01L21/76237 ,  H01L29/735 ,  Y10S148/051 ,  Y10S148/096 ,  Y10S148/115 ,  Y10S148/143 ,  Y10S148/168

Abstract: The invention is a transistor or array thereof and method for producing same in sub-micron dimensions on a silicon substrate doped P or N type by forming slots in spaced apart relation across the substrate to define semi-arrays of V shaped intermediate regions which will become a plurality of transistors. Silicon oxide fills these slots and separates the transistor regions from the substrate. Orthogonal slots divide the semi-arrays into individual transistor active regions which are doped by one of N or P doping introduced into each active regions via the orthogonal slots and driven in to comprise the emitter and collector regions on respective sides of original substrate comprising the base regions. Metallization patterns complete electrical connections to the emitter base and collector regions and silicon oxide substantially covers the periphery of each active region for total isolation. Each transistor may further comprise a doped region called P or N doping extending into and across the top of the base region to reduce space region contact resistance and to provide an electron reflecting potential barrier. Each transistor may further comprise a doped skin of either P or N doping to force electrons or holes toward the center of the base region.

Abstract translation: 本发明是一种晶体管或其阵列，以及通过在衬底上形成间隔开的关系形成槽的方式，在掺杂有P或N型硅衬底的亚微米尺寸上制造该晶体管或其阵列，以限定将形成V形中间区域的半阵列 多个晶体管。 硅氧化物填充这些槽并将晶体管区域与衬底分离。 正交槽将半阵列分成单独的晶体管有源区，其通过正交沟槽引入到每个有源区中的N或P掺杂之一掺杂，并被驱动以在原始衬底的相应侧上包括发射极和集电极区域，该区域包括基极 地区。 金属化图案与发射极基极和集电极区域完全电连接，氧化硅基本上覆盖每个有源区域的周边以进行全部隔离。 每个晶体管还可以包括被称为P或N掺杂的掺杂区域，其延伸到基极区域的顶部并跨过基极区域的顶部，以减小空间区域接触电阻并提供电子反射势垒。 每个晶体管还可以包括P或N掺杂的掺杂表皮，以迫使电子或孔朝向基极区的中心。

公开(公告)号：US4415371A

公开(公告)日：1983-11-15

申请号：US220400

申请日：1980-12-29

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/8224 ,  H01L21/263 ,  H01L21/265 ,  H01L21/306 ,  H01L21/331 ,  H01L21/762 ,  H01L27/082 ,  H01L29/73 ,  H01L29/735 ,  H01L21/22 ,  H01L21/31

CPC classification number: H01L21/30608 ,  H01L21/2633 ,  H01L21/26586 ,  H01L21/76237 ,  H01L29/735

Abstract: An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled motes or slotted regions, wherein the slots are utilized to dope the substrate within the action region. The N type substrate is double energy boron planted through one surface to establish a P region to a given depth. This surface is oxidized and photoresist masked conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. N+ regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy P implanted depth. Drive-in diffusion enlarges the N+ areas for the emitter and collecter and oxidation fills the mote insulating regions around the active area.The oxide is stripped and the P region enhanced to P+ at the surface, with silox being deposited and opened for metal contacts to the P+ region for the base and the emitter and collector regions. The doping profile of the base region provides a potential barrier to minimize the flow of electrons toward the surface because the emitter electrons are channeled through the less heavily doped part of the base region to the collector.

Abstract translation: 通过为由场氧化物填充的微粒或开槽区域围绕的每个晶体管建立微小的有源区，可以在芯片上将数百个器件的阵列同时处理为亚微米尺寸，其中所述槽用于在衬底的作用区域内掺杂。 N型衬底是通过一个表面种植的双能硼，以建立到给定深度的P区。 该表面被氧化并且光致抗蚀剂常规地掩蔽以打开用于离子研磨的槽的ODE或蚀刻到给定深度的ODE。 通过离子注入以使角度的整个深度未掺杂的角度通过离子注入来建立N +区域，而是将掺杂限制在双能量P植入深度内的区域。 驱动扩散扩大了发射器和收集器的N +面积，氧化填充了活动区域周围的微尘绝缘区域。 氧化物被剥离，并且P区在表面增强至P +，其中silox被沉积并打开用于金属接触到用于基极和发射极和集电极区域的P +区域。 基极区域的掺杂分布提供了一个势垒，以最小化电子朝向表面的流动，因为发射极电子通过基极区的较低掺杂部分被引导至集电极。

公开(公告)号：US4389429A

公开(公告)日：1983-06-21

申请号：US393149

申请日：1982-06-28

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  B05D5/12 ,  C23F1/02 ,  H01L21/306

CPC classification number: H01L23/5221 ,  H01L21/7682 ,  H01L23/535 ,  H01L2924/0002

Abstract: The invention includes methods and apparatus for providing relatively long conductors on integrated chips with substantially reduced RC time constants. The preferred mode utilizes a substrate having a metallization pattern wherein etching or milling into the substrate creates a cavity with a metallization conductor disposed in the mouth of the cavity, said cavity being metallized to provide the second conductor. A similar structure may be formed by utilizing orientation dependent etchant which attacks the (111) surface much quicker than the (100) surface to provide an etched V-shaped cavity wherein the first conductor is still an elongated metallization segment in the mouth of the V, and the V is metallized to provide the second conductor. Also, a single conductor, such as the elongated metallization strip may be extended to a conductor on the reverse side of the substrate by providing a pyramid shaped hole from the first conductor through the substrate, which hole is metallized to extend the first conductor to the second conductor via the hole in the substrate.

Abstract translation: 本发明包括用于在集成芯片上提供相当长的导体的方法和装置，具有显着降低的RC时间常数。 优选模式利用具有金属化图案的衬底，其中蚀刻或研磨到衬底中产生具有设置在腔的口中的金属化导体的空腔，所述腔被金属化以提供第二导体。 可以通过利用取向依赖的蚀刻剂来形成类似的结构，所述蚀刻剂比（100）表面更快地攻击（111）表面以提供蚀刻的V形腔，其中第一导体仍然是V的口中的细长金属化段 ，并且V被金属化以提供第二导体。 此外，诸如细长金属化带的单个导体可以通过从第一导体穿过衬底提供金字塔形的孔而延伸到衬底背面的导体，该孔被金属化以将第一导体延伸到 第二导体经由衬底中的孔。

公开(公告)号：US4379307A

公开(公告)日：1983-04-05

申请号：US160031

申请日：1980-06-16

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L27/04

CPC classification number: H01L23/5222 ,  H01L21/76877 ,  H01L23/535 ,  H01L2924/0002

Abstract: The invention includes methods and apparatus for providing relatively long conductors on integrated chips with substantially reduced RC time constants. The preferred mode utilizes a substrate having a metallization pattern wherein etching or milling into the substrate creates a cavity with a metallization conductor disposed in the mouth of the cavity, said cavity being metallized to provide the second conductor. A similar structure may be formed by utilizing orientation dependent etchant which attacks the (111) surface much quicker than the (100) surface to provide an etched V-shaped cavity wherein the first conductor is still an elongated metallization segment in the mouth of the V, and the V is metallized to provide the second conductor. Also, a single conductor, such as the elongated metallization strip may be extended to a conductor on the reverse side of the substrate by providing a pyramid shaped hole from the first conductor through the substrate, which hole is metallized to extend the first conductor to the second conductor via the hole in the substrate.

Abstract translation: 本发明包括用于在集成芯片上提供相当长的导体的方法和装置，具有显着降低的RC时间常数。 优选模式利用具有金属化图案的衬底，其中蚀刻或研磨到衬底中产生具有设置在腔的口中的金属化导体的空腔，所述腔被金属化以提供第二导体。 可以通过利用取向依赖的蚀刻剂来形成类似的结构，所述蚀刻剂比（100）表面更快地攻击（111）表面以提供蚀刻的V形腔，其中第一导体仍然是V的口中的细长金属化段 ，并且V被金属化以提供第二导体。 此外，诸如细长金属化带的单个导体可以通过从第一导体穿过衬底提供金字塔形的孔而延伸到衬底背面的导体，该孔被金属化以将第一导体延伸到 第二导体经由衬底中的孔。