公开(公告)号：US5031014A

公开(公告)日：1991-07-09

申请号：US62007

申请日：1987-06-12

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/762 ,  H01L29/10 ,  H01L29/735

CPC classification number: H01L29/1008 ,  H01L21/26586 ,  H01L21/76237 ,  H01L29/735 ,  H01L2924/0002

Abstract: The invention is a transistor or array thereof and method for producing same in VLSI dimensions on a silicon substrate doped P or N type by forming intersecting slots in spaced apart relation across the substrate to define semi-arrays of V shaped intermediate regions which will become transistors. Silicon oxide fills these slots and separates the transistor regions from the substrate. Orthogonal slots divided the semi-arrays into individual transistor active regions which are doped by one of N or P doping introduced into each active regions via the orthogonal slots and driven in to comprise the emitter and collector regions on respective sides of original substrate comprising the base regions. Metallization patterns complete electrical connections to the emitter base and collector regions and silicon oxide substantially covers the periphery of each active region for total isolation. Each transistor may further comprise a doped region called P or N doping extending into and across the top of the base region underneath the interconnect metallization to reduce space region contact resistance and to provide an electron reflecting potential barrier. Each transistor may further comprise a doped skin of either P or N doping to force electrons toward the center of the base region.

Abstract translation: 本发明是一种晶体管或其阵列及其在掺杂P或N型硅衬底上的VLSI尺寸中的制造方法，其通过在衬底上形成间隔开的关系形成相交槽，以限定将成为晶体管的V形中间区域的半阵列 。 硅氧化物填充这些槽并将晶体管区域与衬底分离。 正交槽将半阵列划分为单独的晶体管有源区，其通过正交沟槽引入到每个有源区中的N或P掺杂之一掺杂并被驱动以在包含基极的原始衬底的相应侧上包括发射极和集电极区域 地区。 金属化图案与发射极基极和集电极区域完全电连接，氧化硅基本上覆盖每个有源区域的周边以进行全部隔离。 每个晶体管还可以包括被称为P或N掺杂的掺杂区域，其延伸到互连金属化之下的基极区域的顶部并跨过互连金属化之下的基极区域的顶部，以减少空间区域接触电阻并提供电子反射势垒。 每个晶体管还可以包括P或N掺杂的掺杂表皮，以迫使电子朝向基极区域的中心。

公开(公告)号：US4497685A

公开(公告)日：1985-02-05

申请号：US544914

申请日：1983-10-24

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/762 ,  H01L27/10 ,  H01L29/8605 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: H01L21/76237 ,  H01L27/101 ,  H01L29/8605 ,  Y10S438/98

Abstract: The invention provides a unique sub-micron dimensioned resistor and methods of making the same, wherein hundreds of such resistors may be fabricated on a single chip with each comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays and subsequent steps directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate. The support is necessary while orthogonal slots are provided permitting access to opposed sides of the active regions for doping from each end, which doping is driven in from both sides to provide a resistor active region to which electrical connections are applied using conventional techniques providing almost complete reduction of the parasitic capacitances because of the total oxide isolation of the active regions from the substrate.The resistors may also be made by forming intersecting slots in spaced apart relation across the substrate to define semi-arrays of V shaped intermediate regions which will become resistors. Silicon oxide fills these slots and separates the resistor regions from the substrate. Orthogonal slots divide the semi-arrays into individual resistor active regions which are optionally doped by one of N or P doping introduced into each active regions via the orthogonal slots and driven in to comprise the resistors.

Abstract translation: 本发明提供了一种独特的亚微米尺寸的电阻器及其制造方法，其中可以在单个芯片上制造数百个这样的电阻器，其中每个包括由场氧化物包围的有源区域，其完全将其与衬底隔离，并且其对操作的影响 。 在衬底中形成的间隔开的槽允许在其中引入取向相关的蚀刻流体，以至少基本上蚀刻基板的有源区的半阵列远离衬底，除了其间隔开的支撑。 氧化用于从衬底直接支撑半阵列和后续步骤，或者通过连接到衬底的半阵列顶部的氧化纤维网。 支撑是必需的，同时提供正交槽，允许从有源区域的相对侧进入用于从每个端部进行掺杂，该掺杂从两侧被驱动以提供电阻器有源区域，使用提供几乎完整的常规技术来施加电连接 由于活性区域与衬底的总氧化物隔离，寄生电容的减小。 电阻器也可以通过在衬底上以间隔开的关系形成相交的槽来形成将形成电阻器的V形中间区域的半阵列。 硅氧化物填充这些槽并将电阻器区域与衬底分离。 正交槽将半阵列划分为单个电阻器有源区，其可选地通过经由正交槽引入到每个有源区中的N或P掺杂中的一个掺杂，并被驱动以包括电阻器。

公开(公告)号：US5025302A

公开(公告)日：1991-06-18

申请号：US62754

申请日：1987-06-16

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/762 ,  H01L21/8222 ,  H01L27/12 ,  H01L29/73

CPC classification number: H01L21/76237 ,  H01L21/26586 ,  H01L21/8222 ,  H01L29/7317 ,  H01L27/1203

Abstract: The invention provides a unique sub-micron dimensioned PNP-type transistor wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots. Substrate oxidation supports the active regions while orthogonal slots are provided permitting access to opposed sides of the active regions for doping N+ which is driven in from one side only while P or P+ is introduced and driven in from both sides, thereby providing a P+ N+N, P+ emitter, base, collector transistor active region to which electrical connections are applied using conventional techniques, providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

Abstract translation: 本发明提供了一种独特的亚微米尺寸的PNP型晶体管，其中可以在单个芯片上制造数百个这样的晶体管，其中每个晶体管包括由场氧化物包围的有源区域，其完全将其与衬底隔离，并且其对操作的影响。 在衬底中制成的槽允许蚀刻抗蚀剂的角度蒸发，以通过经由槽蚀刻而与衬底断开而保护有源区。 衬底氧化支持有源区，同时提供正交槽，允许进入有源区的相对侧用于掺杂N +，其仅在P或P +从两侧引入并驱动时从一侧驱动，从而提供P + N + N，P +发射极，基极，集电极晶体管有源区域，使用常规技术施加电连接，由于有源区域与基板的总氧化物隔离，几乎完全降低了寄生电容和电阻。

公开(公告)号：US4611387A

公开(公告)日：1986-09-16

申请号：US721004

申请日：1985-04-08

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/306 ,  H01L21/331 ,  H01L21/762 ,  H01L29/735 ,  H01L21/461

CPC classification number: H01L29/6625 ,  H01L21/265 ,  H01L21/30608 ,  H01L21/76237 ,  H01L21/76264 ,  H01L29/735

Abstract: The invention provides a unique VLSI dimensioned NPN type transistor and method of making the same, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate. The support is necessary while orthogonal slots are provided permitting access to opposed sides of the active regions for doping n+ from each end, which n+ is driven in from both sides to provide an n+p n+ emitter-base-collector transistor active region to which electrical connections are applied using conventional techniques providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

Abstract translation: 本发明提供了一种独特的VLSI尺寸尺寸的NPN型晶体管及其制造方法，其中可以在单个芯片上制造数百个这样的晶体管，其中每个晶体管包括由场氧化物包围的有源区域，其完全将其与衬底隔离，并且其对 操作。 在衬底中形成的间隔开的槽允许在其中引入取向相关的蚀刻流体，以至少基本上蚀刻基板的有源区的半阵列远离衬底，除了其间隔开的支撑。 氧化用于从衬底直接支撑半阵列，或者通过连接到衬底的半阵列顶部的氧化纤维网。 支撑是必需的，同时提供正交槽，允许进入有源区的相对侧，用于从两端掺杂n +，n +从两侧驱动，以提供n + p n +发射极 - 基极 - 集电极晶体管有源区， 使用常规技术施加电连接，由于活性区域与衬底的总氧化物隔离，几乎完全降低了寄生电容和电阻。

公开(公告)号：US4506283A

公开(公告)日：1985-03-19

申请号：US261435

申请日：1981-05-08

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L27/00 ,  H01L21/762 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01L29/8605

CPC classification number: H01L21/76237 ,  H01L27/101 ,  H01L29/8605

Abstract: The invention provides a unique sub-micron dimensioned resistor and methods of making the same, wherein hundreds of such resistors may be fabricated on a single chip with each comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays and subsequent steps directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate. The support is necessary while orthogonal slots are provided permitting access to opposed sides of the active regions for doping from each end, which doping is driven in from both sides to provide a resistor active region to which electrical connections are applied using conventional techniques providing almost complete reduction of the parasitic capacitances because of the total oxide isolation of the active regions from the substrate.The resistors may also be made by forming intersecting slots in spaced apart relation across the substrate to define semi-arrays of V shaped intermediate regions which will become resistors. Silicon oxide fills these slots and separates the resistor regions from the substrate. Orthogonal slots divide the semi-arrays into individual resistor active regions which are optionally doped by one of N or P doping introduced into each active region via the orthogonal slots and driven in to comprise the resistors.

Abstract translation: 本发明提供了一种独特的亚微米尺寸的电阻器及其制造方法，其中可以在单个芯片上制造数百个这样的电阻器，其中每个包括由场氧化物包围的有源区域，其完全将其与衬底隔离，并且其对操作的影响 。 在衬底中形成的间隔开的槽允许在其中引入取向相关的蚀刻流体，以至少基本上蚀刻基板的有源区的半阵列远离衬底，除了其间隔开的支撑。 氧化用于从衬底直接支撑半阵列和后续步骤，或者通过连接到衬底的半阵列顶部的氧化纤维网。 支撑是必需的，同时提供正交槽，允许从有源区域的相对侧进入用于从每个端部进行掺杂，该掺杂从两侧被驱动以提供电阻器有源区域，使用提供几乎完整的常规技术来施加电连接 由于活性区域与衬底的总氧化物隔离，寄生电容的减小。 电阻器也可以通过在衬底上以间隔开的关系形成相交的槽来形成将形成电阻器的V形中间区域的半阵列。 硅氧化物填充这些槽并将电阻器区域与衬底分离。 正交槽将半阵列分成单独的电阻器有源区，其各自的电阻有源区，其可选地通过经由正交槽引入到每个有源区中的N或P掺杂之一掺杂并被驱动以包括电阻。

公开(公告)号：US5027184A

公开(公告)日：1991-06-25

申请号：US63541

申请日：1987-06-17

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/306 ,  H01L21/331 ,  H01L21/762 ,  H01L29/735

CPC classification number: H01L29/6625 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/76264 ,  H01L29/735 ,  H01L21/76281

Abstract: The invention provides a unique sub-micron dimensioned NPN type transistor, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots. Substrate oxidation supports the active regions while orthogonal slots are provided permitting access to opposed sides of the active regions for doping P+ which is driven in from one side only while N+ is introduced and driven in from both sides, thereby providing an N+ P+P, N+ emitter, base, collector transistor active region to which electrical connections are applied using conventional techniques, providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

Abstract translation: 本发明提供了一种独特的亚微米尺寸的NPN型晶体管，其中可以在单个芯片上制造数百个这样的晶体管，每个晶体管包括由场氧化物包围的有源区域，其完全将其与衬底隔离，并且其对操作的影响。 在衬底中制成的槽允许蚀刻抗蚀剂的角度蒸发，以通过经由槽蚀刻而与衬底断开而保护有源区。 衬底氧化支持有源区，同时提供正交槽，允许进入有源区的相对侧用于掺杂P +，其仅在N +从两侧引入并驱动时从一侧被驱动，从而提供N + P + P， 使用常规技术施加电连接的N +发射极，基极，集电极晶体管有源区，由于活性区域与衬底的总氧化物隔离，几乎完全降低了寄生电容和电阻。

公开(公告)号：US4485551A

公开(公告)日：1984-12-04

申请号：US450308

申请日：1982-12-16

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/306 ,  H01L21/331 ,  H01L21/762 ,  H01L29/735 ,  H01L29/06 ,  H01L21/76

CPC classification number: H01L29/6625 ,  H01L21/265 ,  H01L21/30608 ,  H01L21/76237 ,  H01L21/76264 ,  H01L29/735 ,  Y10S438/973

Abstract: The invention provides a unique sub-micron dimensioned NPN type transistor and method of making the same, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays and subsequent steps directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate. The support is necessary while orthogonal slots are provided permitting access to opposed sides of the active regions for doping n+ from each end, which n+ is driven in from both sides to provide an n+p n+ emitter base collector transistor active region to which electrical connections are applied using conventional techniques providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

Abstract translation: 本发明提供了一种独特的亚微米尺寸的NPN型晶体管及其制造方法，其中可以在单个芯片上制造数百个这样的晶体管，其中每个晶体管包括由场氧化物包围的有源区域，其完全将其与衬底隔离， 对操作的影响。 在衬底中形成的间隔开的槽允许在其中引入取向相关的蚀刻流体，以至少基本上蚀刻基板的有源区的半阵列远离衬底，除了其间隔开的支撑。 氧化用于从衬底直接支撑半阵列和后续步骤，或者通过连接到衬底的半阵列顶部的氧化纤维网。 支撑是必需的，同时提供正交槽，允许进入有源区域的相对侧，用于从两端掺杂n +，n +从两侧驱动，以提供n + p n +发射极基极集电极晶体管有源区，电连接 使用常规技术施加，由于活性区域与基底的总氧化物隔离，几乎完全降低了寄生电容和电阻。

公开(公告)号：US4473834A

公开(公告)日：1984-09-25

申请号：US369858

申请日：1982-04-19

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L33/00 ,  H01L27/14 ,  H01L31/00

CPC classification number: H01L33/0016

Abstract: A light emitting bipolar transistor, adapted to produce light from cathodoluminescence, upon being biased into conduction, the light emitting bipolar transistor being formed on the top surface of a relatively flat semiconductor substrate and having active regions comprising: a collector region, and an emitter region, the collector and emitter regions being of a first conductivity type, and an extended base region of a second conductivity type, the extended base region being interposed between the collector and the emitter regions, and the base region having a coatable surface, a phosphor coating, the phosphor coating covering the base region coatable surface, and respective connections to the collector emitter and base regions; whereby, biasing the transistor into conduction produces an electric field in the base region, the electric field in the base field inducing electrons in the base region to increase energy to a high energy level and to drift, some drifting high energy electrons being scattered into the phosphor coating, thereby impacting the phosphor and producing light by cathodoluminescence.

Abstract translation: 一种发光双极晶体管，适于在阴极发光时产生光，在被偏置成导通时，所述发光双极晶体管形成在相对平坦的半导体衬底的顶表面上并且具有有源区，所述有源区包括：集电极区和发射极区 ，所述集电极和发射极区域是第一导电类型，以及第二导电类型的延伸基极区域，所述延伸基极区域介于所述集电极和发射极区域之间，并且所述基极区域具有可涂覆表面，所述荧光体涂层 ，覆盖基底区域可涂覆表面的荧光体涂层，以及到集电极发射极和基极区域的各自连接; 由此，将晶体管偏置为导通在基极区域中产生电场，基极中的电场在基极区域中感应电子以将能量增加到高能量水平并漂移，一些漂移的高能电子被散射到 荧光粉涂层，从而影响荧光体并通过阴极发光产生光。

公开(公告)号：US4466178A

公开(公告)日：1984-08-21

申请号：US277380

申请日：1981-06-25

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L21/762 ,  H01L21/8222 ,  H01L27/102 ,  H01L29/735 ,  H01L21/22 ,  H01L21/31

CPC classification number: H01L29/735 ,  H01L21/26586 ,  H01L21/76237 ,  H01L21/8222 ,  H01L27/1022

Abstract: An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled moats or slotted regions, wherein the slots are utilized to dope the substrate within the active region. The P type substrate is double energy arsenic planted through one surface to establish a N region to a given depth. This surface is oxidized and photoresist masked conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. P+ regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy N implanted depth. Drive-in diffusion enlarges the P+ areas for the emitter and collector and oxidation fills the moat insulating regions around the active area.The oxide is stripped and the N region enhanced to N+ at the surface, with silox being deposited and opened for metal contacts to the N+ region for the base and the emitter and collector regions. The doping profile of the base region provides a potential barrier to minimize the flow of electrons toward the surface because the emitter electrons are channeled through the less heavily doped part of the base region to the collector.

Abstract translation: 通过为由场氧化物填充的沟槽或开槽区域围绕的每个晶体管建立微小的有源区，可以在芯片上将数百个器件的阵列同时处理为亚微米尺寸，其中所述槽用于将衬底掺杂在有源区域内。 P型底物是通过一个表面种植的双能砷，以建立给定深度的N区。 该表面被氧化并且光致抗蚀剂常规地掩蔽以打开用于离子研磨的槽的ODE或蚀刻到给定深度的ODE。 通过离子注入以使得槽的整个深度不掺杂的角度通过离子注入来建立P +区域，而是将掺杂限制在双能量N注入深度内的区域。 驱动扩散扩大了发射极和集电极的P +区域，氧化填充了有源区域周围的护城河绝缘区域。 氧化物被剥离，并且N区在表面增强至N +，其中silox被沉积并打开用于金属接触到用于基极和发射极和集电极区域的N +区域。 基极区域的掺杂分布提供了一个势垒，以最小化电子朝向表面的流动，因为发射极电子通过基极区的较低掺杂部分被引导至集电极。

公开(公告)号：US4369406A

公开(公告)日：1983-01-18

申请号：US146928

申请日：1980-05-05

Applicant: Sidney I. Soclof ,  Michael T. Elliott

Inventor： Sidney I. Soclof ,  Michael T. Elliott

IPC: H01L27/22 ,  H01L29/82 ,  G01R33/02 ,  H01L43/00

CPC classification number: H01L29/82 ,  H01L27/22

Abstract: A device for reading information representing magnetization patterns on a medium by means of a time-of-flight magnetotransistor detector. The time-of-flight magnetotransistor detector consists of a bipolar transistor implemented on a semiconductor surface which is in a magnetic flux coupling with a plurality of magnetization patterns. Such magnetization patterns which may be generated by a magnetic bubble domain on an adjacent bubble domain device or by a magnetized region on an adjacent media such as a magnetic tape or disk. The magnetotransistor detector consists of an emitter region, an elongated base region, and a collector region, and a twin-lead thin-film transmission line in capacitive coupling with the base region of the magnetotransistor. The presence of a magnetic field in the base region creates a Hall voltage which produces a pulse on the transmission line.

Abstract translation: 一种用于通过飞行时间磁控晶体管检测器读取表示介质上的磁化模式的信息的装置。 飞行时间磁控晶体管检测器由实现在与多个磁化模式耦合的磁通中的半导体表面上实现的双极晶体管组成。 这种磁化模式可以由相邻气泡区域装置上的磁性气泡区域或相邻介质如磁带或磁盘上的磁化区域产生。 磁电晶体管检测器由发射极区域，细长基极区域和集电极区域构成，以及与磁电晶体管的基极区域电容耦合的双引线薄膜传输线。 在基极区域中存在磁场产生在传输线上产生脉冲的霍尔电压。