公开(公告)号：US06463516B1

公开(公告)日：2002-10-08

申请号：US09663765

申请日：2000-09-18

Applicant: Nancy S. Leong ,  Johnny C. Chen ,  Tiao-Hua Kuo ,  Kazuhiro Kurihara

Inventor： Nancy S. Leong ,  Johnny C. Chen ,  Tiao-Hua Kuo ,  Kazuhiro Kurihara

IPC: G06F1202

CPC classification number: G06F12/0246 ,  G11C16/08

Abstract: A variable sector size for a flash memory device is disclosed. The total available memory of the flash memory device is divided into sub-units. Each sub-unit has a pre-decoder coupled with it to enable operations on the memory within that sub-unit. A sector size control register is coupled with pre-decoder enabling logic which is coupled with the pre-decoders. The sector size control register and pre-decoder enabling logic determines how many pre-decoders, and therefore how many sub-units, are activated at a given time for a given memory operation.

Abstract translation: 公开了一种用于闪存器件的可变扇区大小。 闪存设备的总可用内存分为子单元。 每个子单元具有与其耦合的预解码器以使得能够对该子单元内的存储器进行操作。 扇区大小控制寄存器与预解码器使能逻辑耦合，该逻辑与预解码器耦合。 扇区大小控制寄存器和预解码器使能逻辑确定在给定存储器操作的给定时间内激活了多少个预解码器，因此有多少个子单元被激活。

公开(公告)号：US06331950B1

公开(公告)日：2001-12-18

申请号：US09421757

申请日：1999-10-19

Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Johnny C. Chen

Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Johnny C. Chen

IPC: G11C700

CPC classification number: G11C16/22 ,  G11C16/30

Abstract: An input circuit for a flash memory device is disclosed. The input circuit includes an input for receiving a voltage signal from an external source representing a digital logic signal. The input circuit further includes a pull up circuit which is coupled with the input and pulls the input to a high logic level when the input is not connected to any external source.

Abstract translation: 公开了一种用于闪速存储器件的输入电路。 输入电路包括用于从表示数字逻辑信号的外部源接收电压信号的输入端。 输入电路还包括与输入耦合的上拉电路，并且当输入未连接到任何外部源时将输入拉到高逻辑电平。

公开(公告)号：US06208558B1

公开(公告)日：2001-03-27

申请号：US09293006

申请日：1999-04-16

Applicant: Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

Inventor： Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

IPC: C11C1604

CPC classification number: G11C16/10 ,  G11C16/16

Abstract: An acceleration circuit for fast programming and fast chip erase of a non-volatile memory array (46) comprises an acceleration input (2) coupled to a triggering circuit (4) which is capable of generating fast program and fast chip erase commands. In an embodiment, the triggering circuit (4) comprises a high voltage detector (6), which is coupled to the acceleration input (2), and a logic circuit (8), which is coupled to the high voltage detector (6) and has a plurality of command write inputs (10). In a further embodiment, the acceleration voltage is reduced by a regulator (52) to generate a regulated voltage, which is supplied to the memory cells (72a, 72b, 74a, 74b, . . . ) in fast program and fast chip erase modes.

Abstract translation: 用于非易失性存储器阵列（46）的快速编程和快速芯片擦除的加速电路包括耦合到能够产生快速程序和快速芯片擦除命令的触发电路（4）的加速度输入（2）。 在一个实施例中，触发电路（4）包括耦合到加速输入端（2）的高电压检测器（6）和耦合到高压检测器（6）的逻辑电路（8） 具有多个命令写入输入（10）。 在另一实施例中，通过调节器（52）减小加速电压，以产生以快速程序和快速芯片擦除模式提供给存储单元（72a，72b，74a，74b ...）的调节电压 。

公开(公告)号：US6125056A

公开(公告)日：2000-09-26

申请号：US291865

申请日：1999-04-14

Applicant: Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

Inventor： Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10

Abstract: A method for fast programming of non-volatile memory cells in a non-volatile memory array comprises the steps of providing an acceleration voltage greater than the internal pump voltage supplied by a conventional internal drain pump, providing a program write command, and coupling the acceleration voltage to provide a programming current to all of the bit lines selected to be programmed at a time. In an embodiment, the acceleration voltage is reduced to a drain voltage before it is applied to the drains of the memory cells. In an embodiment in which the flash memory cells comprise typical dual-gate NOR devices, the acceleration voltage is in the range of about 7 V to about 10 V, and the drain voltage is on the order of about 5 V. The sources of the memory cells are grounded during the fast programming operation. In a further embodiment, the method further comprises the steps of detecting the acceleration voltage, generating an acceleration voltage indicator signal in response to the presence of the acceleration voltage, and generating a fast program write command in response to the acceleration voltage indicator signal and the program write command to set the flash memory cells in a fast program mode.

Abstract translation: 用于在非易失性存储器阵列中快速编程非易失性存储器单元的方法包括以下步骤：提供大于由常规内部排水泵提供的内部泵浦电压的加速电压，提供程序写入命令，以及耦合加速度 电压以将编程电流提供给所选择的一次编程的位线。 在一个实施例中，加速电压在被施加到存储器单元的漏极之前被减小到漏极电压。 在闪存单元包括典型的双栅极NOR器件的实施例中，加速电压在约7V至约10V的范围内，漏极电压约为5V左右。源 存储单元在快速编程操作期间接地。 在另一实施例中，该方法还包括以下步骤：检测加速电压，响应加速电压的存在产生加速电压指示信号，并响应加速电压指示信号产生快速程序写命令 程序写入命令以快速程序模式设置闪存单元。