公开(公告)号：US06463516B1

公开(公告)日：2002-10-08

申请号：US09663765

申请日：2000-09-18

申请人： Nancy S. Leong ,  Johnny C. Chen ,  Tiao-Hua Kuo ,  Kazuhiro Kurihara

发明人： Nancy S. Leong ,  Johnny C. Chen ,  Tiao-Hua Kuo ,  Kazuhiro Kurihara

IPC分类号： G06F1202

CPC分类号： G06F12/0246 ,  G11C16/08

摘要： A variable sector size for a flash memory device is disclosed. The total available memory of the flash memory device is divided into sub-units. Each sub-unit has a pre-decoder coupled with it to enable operations on the memory within that sub-unit. A sector size control register is coupled with pre-decoder enabling logic which is coupled with the pre-decoders. The sector size control register and pre-decoder enabling logic determines how many pre-decoders, and therefore how many sub-units, are activated at a given time for a given memory operation.

摘要翻译： 公开了一种用于闪存器件的可变扇区大小。 闪存设备的总可用内存分为子单元。 每个子单元具有与其耦合的预解码器以使得能够对该子单元内的存储器进行操作。 扇区大小控制寄存器与预解码器使能逻辑耦合，该逻辑与预解码器耦合。 扇区大小控制寄存器和预解码器使能逻辑确定在给定存储器操作的给定时间内激活了多少个预解码器，因此有多少个子单元被激活。

公开(公告)号：US20140020967A1

公开(公告)日：2014-01-23

申请号：US13816415

申请日：2012-03-13

申请人： Kouji Nishiyama ,  Kazuhiro Kurihara ,  Tetsuya Okuyama

发明人： Kouji Nishiyama ,  Kazuhiro Kurihara ,  Tetsuya Okuyama

IPC分类号： B66F9/075

CPC分类号： B66F9/07572 ,  B60K1/04 ,  B60K2001/0422 ,  B60K2001/0455 ,  B60K2001/0466 ,  B60Y2200/15 ,  B66F9/0754

摘要： A battery-powered forklift including a fork placed at an anterior portion of a vehicle body, and a counter weight placed at a posterior portion of the vehicle body, the battery-powered forklift running by electric power of a battery mounted on the vehicle body, wherein a concave portion that is open in a longitudinal direction is formed at an upper surface of the counter weight, the battery is mounted on a position above a rear wheel of the vehicle body while at least a part of the battery overlaps with the counter weight, and the battery is removable toward a rear of the vehicle body through the concave portion of the counter weight.

摘要翻译： 一种电池供电的叉车，包括放置在车身前部的叉子，以及放置在车体后部的配重，所述电池供电的叉车由安装在车体上的电池的电力运行， 其特征在于，在所述配重的上表面形成有在长度方向上开口的凹部，所述电池被安装在所述车体的后轮上方的位置，同时所述电池的至少一部分与所述配重重叠 并且电池通过配重的凹部朝向车体的后部移除。

公开(公告)号：US08379472B2

公开(公告)日：2013-02-19

申请号：US13155278

申请日：2011-06-07

申请人： Hiroaki Wada ,  Kazuhiro Kurihara

发明人： Hiroaki Wada ,  Kazuhiro Kurihara

IPC分类号： G11C5/14

CPC分类号： G11C16/30 ,  G11C5/147 ,  H04N5/23241

摘要： The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

公开(公告)号：US07903473B2

公开(公告)日：2011-03-08

申请号：US12508319

申请日：2009-07-23

申请人： Hiroki Murakami ,  Kazuhiro Kurihara

发明人： Hiroki Murakami ,  Kazuhiro Kurihara

IPC分类号： G11C16/04

CPC分类号： G11C11/413 ,  G11C16/102 ,  G11C16/105

摘要： A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.

公开(公告)号：US07206241B2

公开(公告)日：2007-04-17

申请号：US11126558

申请日：2005-05-11

申请人： Kazunari Kido ,  Yasushi Kasa ,  Minoru Yamashita ,  Kazuhiro Kurihara ,  Hiroaki Wada

发明人： Kazunari Kido ,  Yasushi Kasa ,  Minoru Yamashita ,  Kazuhiro Kurihara ,  Hiroaki Wada

IPC分类号： G11C7/02

CPC分类号： G11C16/12 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3445 ,  G11C16/3459

摘要： The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.

摘要翻译： 本发明的半导体器件包括至少一个编程状态的虚拟单元，其近似位于参考单元阵列的边缘。 因此，当读取参考单元阵列的边缘上的单元的数据时，泄漏电流不流动。 位于参考单元阵列中心周围的存储单元具有编程状态的相邻单元，并且当从所有参考单元读出数据时，可以防止泄漏电流。 因此，能够稳定地供给基准电流。

公开(公告)号：US06975543B2

公开(公告)日：2005-12-13

申请号：US11085133

申请日：2005-03-22

申请人： Kazuhiro Kurihara

发明人： Kazuhiro Kurihara

IPC分类号： G11C16/06 ,  G11C16/10 ,  G11C16/28 ,  G11C16/34

CPC分类号： G11C16/28 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3454

摘要： A nonvolatile semiconductor memory device includes nonvolatile memory cells each configured to store 2-bit information per memory cell, and a control circuit configured to verify with a first threshold one or more bits subjected to writing of new data and to verify with a second threshold one or more bits subjected to refreshing of existing data in a program operation that performs the writing of new data and the refreshing of existing data simultaneously with respect to the nonvolatile memory cells, the second threshold being lower than the first threshold.

摘要翻译： 非易失性半导体存储器件包括非易失性存储单元，每个非易失性存储单元被配置为存储每个存储单元的2位信息;以及控制电路，被配置为以第一阈值验证经受新数据写入的一个或多个位，并且以第二阈值1 或更多位在执行新数据的写入和与非易失性存储单元同时刷新现有数据的程序操作中刷新现有数据，第二阈值低于第一阈值。

公开(公告)号：US20050254299A1

公开(公告)日：2005-11-17

申请号：US11127713

申请日：2005-05-12

申请人： Yasuhiko Tanuma ,  Kazuhiro Kurihara

发明人： Yasuhiko Tanuma ,  Kazuhiro Kurihara

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/16

摘要： A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal.

摘要翻译： 半导体器件包括具有连接到本地字线的存储器单元的扇区，选择扇区的解码器，以及在擦除所选择的扇区时产生使与选择的扇区相关联的解码器中的对应的一个解码器暂时地产生的控制信号的电路 未选择 每个扇区包括一个上拉晶体管，该上拉晶体管经由相应的解码器之一经由连接扇区的全局字线对应的一个驱动本地字线之一，并且上拉晶体管由 控制信号。

公开(公告)号：US20050162911A1

公开(公告)日：2005-07-28

申请号：US11085496

申请日：2005-03-22

申请人： Kazuhiro Kurihara

发明人： Kazuhiro Kurihara

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C11/34 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16

CPC分类号： G11C8/08 ,  G11C8/12 ,  G11C16/08

摘要： A nonvolatile semiconductor memory device is disclosed that comprises plural sectors each including a memory cell array, plural word line drivers provided in each one of the sectors to drive respective word lines, and sector switches provided one for each sector. The sector switches are connected to the plural word line drivers in the corresponding sector, adapted to provide a negative voltage to be applied to the word lines to the plural word line drivers when the corresponding sector is selected for an erase operation. The sector switches only include transistors directly connected to an output signal line to provide the negative voltage to the word line drivers. A decoding circuit shared by one or more sectors is adapted to control the sector switches to allow a sector switch in a selected sector to output the negative voltage and allow a sector switch in an unselected sector to output a voltage different from the negative voltage.

摘要翻译： 公开了一种非易失性半导体存储器件，其包括多个扇区，每个扇区各自包括存储单元阵列，设置在每个扇区中的多个字线驱动器以驱动相应的字线，以及为每个扇区提供一个扇区开关。 扇区开关连接到相应扇区中的多个字线驱动器，适于在为擦除操作选择相应的扇区时提供要施加到多个字线驱动器的字线的负电压。 扇区开关仅包括直接连接到输出信号线的晶体管，以向字线驱动器提供负电压。 由一个或多个扇区共享的解码电路适于控制扇区开关以允许所选扇区中的扇区切换输出负电压并允许未选择扇区中的扇区切换输出不同于负电压的电压。

公开(公告)号：US06813735B1

公开(公告)日：2004-11-02

申请号：US09676623

申请日：2000-10-02

申请人： Kazuhiro Kurihara ,  Pau-Ling Chen

发明人： Kazuhiro Kurihara ,  Pau-Ling Chen

IPC分类号： G11C2900

CPC分类号： G11C29/76 ,  G11C16/0491 ,  G11C29/846

摘要： The present invention discloses methods and systems of accomplishing I/O-based redundancy for a memory device that includes two-bit memory cells. The memory device includes a core two-bit memory cell array and a redundant two-bit memory cell array. The configuration of the core two-bit memory cell array is non-uniform such that the two-bit memory cells therein are not arranged in a sequential order. Due to the non-uniform configuration, I/O based redundancy is accomplished by decoding the addresses with a redundant Y-decoder circuit and translating the addresses using an address translation circuit. The translated addresses identify the location of the two-bit memory cells within the non-uniform core two-bit memory cell array. The decoding of the addresses configures the redundant two-bit memory cell array to provide a configuration that matches the two-bit memory cells in the location identified by the translated address.

摘要翻译： 本发明公开了一种为包含2位存储单元的存储器件完成基于I / O的冗余的方法和系统。 存储器件包括核心的两位存储单元阵列和冗余的两位存储单元阵列。 核心2位存储单元阵列的配置是不均匀的，使得其中的2位存储单元不按顺序排列。 由于不均匀配置，基于I / O的冗余是通过使用冗余Y解码器电路解码地址并使用地址转换电路翻译地址来实现的。 翻译的地址标识不均匀核心2位存储单元阵列内的两位存储单元的位置。 地址的解码配置冗余的两比特存储单元阵列以提供与由翻译的地址标识的位置中的两比特存储器单元匹配的配置。

公开(公告)号：US06744666B1

公开(公告)日：2004-06-01

申请号：US10243792

申请日：2002-09-12

申请人： Santosh Yachareni ,  Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Pau-Ling Chen

发明人： Santosh Yachareni ,  Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Pau-Ling Chen

IPC分类号： G11C1134

CPC分类号： G11C16/10 ,  G11C2216/14 ,  G11C2216/16

摘要： Embodiments of the present invention are directed to a method and system to minimize page programming time for page programmable memory devices. In one embodiment, the present invention comprises program logic that programs a page programmable memory device with a plurality of words during a page programming cycle and a detector coupled to the program logic that identifies a particular word in that plurality of words which does not require programming. When the detector identifies a particular word which does not require programming, it sends an indication to the program logic component which, in response to the signal, reduces the length of the page programming cycle.

摘要翻译： 本发明的实施例涉及一种使页面可编程存储器件的页面编程时间最小化的方法和系统。 在一个实施例中，本发明包括在页面编程周期期间用多个单词编程页面可编程存储器件的程序逻辑和耦合到程序逻辑的检测器，该程序逻辑识别出不需要编程的多个单词中的特定单词 。 当检测器识别不需要编程的特定字时，它向程序逻辑组件发送指示，该程序逻辑组件响应于该信号减少了页面编程周期的长度。