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    Multi-bit flash memory device having improved program rate
    1.
    发明授权
    Multi-bit flash memory device having improved program rate 有权
    具有改进的程序速率的多位闪存设备

    公开(公告)号：US07433228B2

    公开(公告)日：2008-10-07

    申请号：US11229519

    申请日：2005-09-20

    Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

    Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

    IPC: G11C16/04

    CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/10

    Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

    Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源 区域和漏极区域。 该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在 第二个地区的利率要高得多。

    Multiple purpose bus for a simultaneous operation flash memory device
    3.
    发明授权
    Multiple purpose bus for a simultaneous operation flash memory device 失效
    多用途总线，用于同时运行闪存设备

    公开(公告)号：US06571307B1

    公开(公告)日：2003-05-27

    申请号：US09421758

    申请日：1999-10-19

    Applicant: Tiao-Hua Kuo ,  Nancy S. Leong ,  Takao Akagoi ,  Yasushi Kasa

    Inventor： Tiao-Hua Kuo ,  Nancy S. Leong ,  Takao Akagoi ,  Yasushi Kasa

    IPC: G06F1300

    CPC classification number: G11C16/06 ,  G11C2216/22

    Abstract: A multiple purpose bus for a flash memory device that allows six sets of data signals to utilize the bus. The multiple purpose bus includes sixteen circuit lines that extend from one end of the memory device to another end of the memory device. Control signals that correspond to each set of data signals couple the sets of data signals to the circuit lines. A grounding circuit is provided that couples the circuit lines to a ground when none of the sets of data signals are utilizing the multiple purpose bus.

    Abstract translation: 用于闪存设备的多用途总线，允许六组数据信号利用总线。 多用途总线包括从存储器件的一端延伸到存储器件的另一端的十六条电路线。 对应于每组数据信号的控制信号将数据信号组耦合到电路线。 当没有一组数据信号正在利用多用途总线时，提供将电路线耦合到地的接地电路。

    Array VT mode implementation for a simultaneous operation flash memory device
    4.
    发明授权
    Array VT mode implementation for a simultaneous operation flash memory device 失效
    阵列VT模式实现用于同时运行的闪存设备

    公开(公告)号：US06550028B1

    公开(公告)日：2003-04-15

    申请号：US09421470

    申请日：1999-10-19

    Applicant: Takao Akaogi ,  Tiao-Hua Kuo ,  Fan W. Lai

    Inventor： Takao Akaogi ,  Tiao-Hua Kuo ,  Fan W. Lai

    IPC: G11C2900

    CPC classification number: G11C29/028 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C2029/0403

    Abstract: An array threshold voltage test mode for a flash memory device is disclosed. During the test mode, a test voltage is routed directly to the gates of the flash memory transistors selected by a given address. If the test voltage causes the selected transistors to change state by crossing their threshold voltage level, the change will be reflected in the data outputs of the device. By varying the test voltages and the addresses and monitoring the data outputs, the array threshold voltage distribution can be determined for the entire device.

    Abstract translation: 公开了一种用于闪存器件的阵列阈值电压测试模式。 在测试模式期间，测试电压直接路由到由给定地址选择的闪存晶体管的栅极。 如果测试电压导致所选择的晶体管通过交叉其阈值电压电平来改变状态，则该变化将反映在器件的数据输出中。 通过改变测试电压和地址并监视数据输出，可以为整个器件确定阵列阈值电压分布。

    Unlock bypass program mode for non-volatile memory
    5.
    发明授权
    Unlock bypass program mode for non-volatile memory 失效
    为非易失性存储器解锁旁路程序模式

    公开(公告)号：US6157567A

    公开(公告)日：2000-12-05

    申请号：US70160

    申请日：1998-04-30

    Applicant: Tiao-Hua Kuo ,  Eric Itakura ,  May Xie ,  Nancy Leong

    Inventor： Tiao-Hua Kuo ,  Eric Itakura ,  May Xie ,  Nancy Leong

    IPC: G11C16/10 ,  G11C16/04

    CPC classification number: G11C16/10

    Abstract: The invention is directed to a single power supply pin non-volatile memory device that increases programming speed by providing for two-cycle programming. The invention maintains measures to prevent accidental user overwrites and maintains JEDEC standard compatibility. To provide for two-cycle programming, a three-cycle unlock bypass command is first sent, in one embodiment, after which a plurality of consecutive two-cycle program commands can be sent.

    Abstract translation: 本发明涉及通过提供两周期编程来提高编程速度的单个电源引脚非易失性存储器件。 本发明保持措施以防止意外用户重写并维护JEDEC标准的兼容性。 为了提供双周期编程，首先发送三周期解锁旁路命令，在一个实施例中，之后可以发送多个连续的两周期程序命令。

    Bank architecture for a non-volatile memory enabling simultaneous reading and writing
    6.
    发明授权
    Bank architecture for a non-volatile memory enabling simultaneous reading and writing 失效
    用于非易失性存储器的银行体系结构，可同时读写

    公开(公告)号：US5867430A

    公开(公告)日：1999-02-02

    申请号：US772131

    申请日：1996-12-20

    Applicant: Johnny C. Chen ,  Chung K. Chang ,  Tiao-Hua Kuo ,  Takao Akaogi

    Inventor： Johnny C. Chen ,  Chung K. Chang ,  Tiao-Hua Kuo ,  Takao Akaogi

    IPC: G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G06F12/00 ,  G11C7/00

    CPC classification number: G11C16/10 ,  G11C2216/22

    Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation. Power is supplied for each of the read and write operations via an internal multiplexed multi power supply source that provides an amount of power needed based on the memory operation being performed.

    Abstract translation: 闪存器件分为两个或更多个存储体。 每个银行都包括一些行业。 每个扇区包括闪存单元。 每个存储体都有一个解码器，可选择性地从输入地址缓冲区或由内部状态机控制的内部地址排序器接收地址。 每个存储体的输出数据可以传送到读出读出放大器或校验读出放大器。 读出放大器连接到输出缓冲器，而验证放大器连接到状态机。 当一个银行收到一个写入命令时，内部状态机将进行控制并启动程序或擦除操作。 当一个银行忙于编程或擦除操作时，可以访问另一个存储体进行读取操作。 通过内部复用多电源提供每个读取和写入操作的电源，该内部复用多电源提供基于正在执行的存储器操作所需的功率量。

    Fast chip erase mode for non-volatile memory
    8.
    发明授权
    Fast chip erase mode for non-volatile memory 有权
    用于非易失性存储器的快速芯片擦除模式

    公开(公告)号：US6101129A

    公开(公告)日：2000-08-08

    申请号：US291984

    申请日：1999-04-14

    Applicant: Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

    Inventor： Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

    IPC: G11C16/16 ,  G11C16/04

    CPC classification number: G11C16/16

    Abstract: A method for fast chip erase of memory cells in a non-volatile memory array comprises the steps of providing an acceleration voltage greater than the internal pump voltage supplied by a conventional internal voltage supply pump, providing an erase write command, and performing a fast erase operation on the memory cells, comprising the step of coupling the acceleration voltage to the sources of the memory cells in a plurality of sectors simultaneously. In an embodiment, a fast preprogramming operation is performed on the memory cells prior to the step of performing the fast erase operation in the fast chip erase mode. In a further embodiment, a fast weak programming (APDE) operation is performed on the memory cells subsequent to the step of performing the fast erase operation in the fast chip erase mode. In an additional embodiment, the step of performing the fast erase operation further comprises the steps of detecting the acceleration voltage, generating an acceleration voltage indicator signal in response to the detection of the acceleration voltage, and generating a fast chip erase write command in response to the acceleration voltage indicator signal and the erase write command.

    Abstract translation: 用于在非易失性存储器阵列中快速擦除存储器单元的方法包括以下步骤：提供大于由常规内部电压供应泵提供的内部泵浦电压的加速电压，提供擦除写入命令，以及执行快速擦除 包括将加速电压与多个扇区中的存储单元的源极同时耦合的步骤。 在一个实施例中，在以快速擦除擦除模式执行快速擦除操作的步骤之前，对存储器单元执行快速预编程操作。 在另一实施例中，在执行快速擦除擦除模式中的快速擦除操作的步骤之后，对存储器单元执行快速弱编程（APDE）操作。 在另外的实施例中，执行快速擦除操作的步骤还包括以下步骤：检测加速电压，响应于加速电压的检测产生加速电压指示信号，并响应于 加速电压指示信号和擦除写命令。

    Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture
    9.
    发明授权
    Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture 有权
    银行选择器电路，用于具有灵活的银行分区架构的同时操作的闪存设备

    公开(公告)号：US06633949B2

    公开(公告)日：2003-10-14

    申请号：US09892431

    申请日：2001-06-26

    Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    IPC: G06F1200

    CPC classification number: G11C8/12 ,  G11C16/08

    Abstract: A bank selector encoder comprises a partition indicator circuit having a plurality of partition boundary indicator terminals, a plurality of inverters arranged in a plurality of columns, with each column of the inverters coupled to a respective one of a plurality of columns of ROM cells in a ROM array and a plurality of bank selector code outputs coupled to respective columns of the inverters. The partition boundary indicator terminals are capable of designating a memory partition boundary to identify an upper memory bank and a lower memory bank. The bank selector encoder is capable of generating an identifying bank selector code for each of a plurality of the predetermined memory partition boundaries. The bank selector encoder outputs code bits of a bank selector code based upon the partition boundary indicator terminals.

    Abstract translation: 存储体选择器编码器包括具有多个分区边界指示符终端的分区指示器电路，多列排列的多个反相器，其中每列反相器耦合到多列ROM单元的相应一列 ROM阵列和耦合到反相器的各列的多个存储体选择器代码输出。 分区边界指示符终端能够指定存储器分区边界以识别上部存储体和下部存储体。 存储体选择器编码器能够为多个预定的存储分区边界中的每一个生成识别库选择器代码。 存储体选择器编码器基于分区边界指示符终端输出存储体选择器代码的代码位。

    Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture
    10.
    发明授权
    Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture 有权
    银行选择器电路，用于具有灵活的银行分区架构的同时操作的闪存设备

    公开(公告)号：US06275894B1

    公开(公告)日：2001-08-14

    申请号：US09159489

    申请日：1998-09-23

    Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

    IPC: G11C1604

    CPC classification number: G11C8/12 ,  G11C16/08

    Abstract: A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option 18, a bank selector encoder 2 coupled to receive a memory partition indicator signal from the memory boundary option 18, and a bank selector decoder 3 coupled to receive a bank selector code from the bank selector encoder 2. The decoder 3, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

    Abstract translation: 一种用于具有灵活存储体分区架构的同步操作闪速存储器件的存储体选择器电路包括存储器边界选项18，耦合以从存储器边界选项18接收存储器分区指示符信号的存储体选择器编码器2以及存储体选择器解码器3 耦合以从存储体选择器编码器2接收存储体选择器代码。解码器3在接收到存储器地址时输出存储体选择器输出信号，以将同时操作中的存储器地址指向下存储体或较高存储体 闪存设备，根据所选择的内存分区边界。

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