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公开(公告)号：US10394721B2
公开(公告)日：2019-08-27
申请号：US15365686
申请日：2016-11-30
发明人： Gajinder Panesar , Rupert Baines , Iain Robertson
摘要： An integrated circuit, having a security supervision system, comprising a plurality of functional circuit blocks interconnected to collectively performing data processing tasks, one or more communication adaptors, having: (i) a hardware interconnection to the functional circuit blocks, whereby the communication adaptor senses the state and/or activity of the functional circuit block; (ii) memory storing definitions of state and/or activity of functional circuit block and actions for each definition; and (iii) processing circuitry comparing the state and/or activity of the functional block with each definition, such that when state and/or activity of the functional block corresponding to a stored definition is detected, perform the corresponding action. The memory stores a definition of state and/or activity characteristic of insecure operation of the functional circuit block and a corresponding action to partially disabling the functional circuit block and/or (ii) causing a message to be transmitted to a destination off the integrated circuit.
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公开(公告)号：US20170153988A1
公开(公告)日：2017-06-01
申请号：US15365686
申请日：2016-11-30
发明人： Gajinder Panesar , Rupert Baines , Iain Robertson
IPC分类号： G06F12/14
CPC分类号： G06F12/1416 , G06F12/1408 , G06F21/562 , G06F21/566 , G06F2212/1052 , G06F2212/402
摘要： An integrated circuit, having a security supervision system, comprising a plurality of functional circuit blocks interconnected to collectively performing data processing tasks, one or more communication adaptors, having: (i) a hardware interconnection to the functional circuit blocks, whereby the communication adaptor senses the state and/or activity of the functional circuit block; (ii) memory storing definitions of state and/or activity of functional circuit block and actions for each definition; and (iii) processing circuitry comparing the state and/or activity of the functional block with each definition, such that when state and/or activity of the functional block corresponding to a stored definition is detected, perform the corresponding action. The memory stores a definition of state and/or activity characteristic of insecure operation of the functional circuit block and a corresponding action to partially disabling the functional circuit block and/or (ii) causing a message to be transmitted to a destination off the integrated circuit.
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公开(公告)号：US09424166B2
公开(公告)日：2016-08-23
申请号：US14251260
申请日：2014-04-11
IPC分类号： G06F11/00 , G06F11/36 , G01R31/317 , G01R31/3177
CPC分类号： G06F11/3656 , G01R31/31705 , G01R31/31721 , G01R31/31723 , G01R31/3177 , G06F11/36 , G06F11/3648
摘要： An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.
摘要翻译： 一种集成电路芯片装置，包括：系统电路; 调试电路被配置为调试系统电路，调试电路被分段成区域; 其中所述调试电路包括被配置为将调试消息通过区域从所述互连结构的区域入口节点路由到所述互连结构的区域出口节点的互连结构; 并且其中所述调试电路被配置为在接收到比指定长度短的区域入口节点处的调试消息时，通过将所述调试消息的长度增加到所述指定长度来修改所述调试消息以形成修改的调试消息。
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公开(公告)号：US20150377965A1
公开(公告)日：2015-12-31
申请号：US14843745
申请日：2015-09-02
IPC分类号： G01R31/317
CPC分类号： G01R31/31705 , G01R31/31721 , G06F1/24 , G06F1/26 , G06F1/30 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3246 , G06F1/325 , G06F1/3287 , G06F11/263 , G06F11/267 , G06F11/36 , G06F11/362 , G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F15/7807
摘要： Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.
摘要翻译： 粗略地描述了一种对集成电路芯片的一部分断电的方法，该集成电路芯片的部分包括多个外围电路，每个外围电路连接到相应的调试单元，该方法包括：在断电之前， 从所述调试单元的每个调试单元的配置信息中提取所述调试单元的配置信息; 在集成电路芯片的部分断电期间将调试单元的配置信息存储在集成电路芯片上的存储器中; 并且在上电时，在恢复该调试单元和连接到该调试单元的外围电路的操作之前将每个调试单元的配置信息恢复到该调试单元。
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公开(公告)号：US20150268302A1
公开(公告)日：2015-09-24
申请号：US14251260
申请日：2014-04-11
IPC分类号： G01R31/317 , G01R31/3177
CPC分类号： G06F11/3656 , G01R31/31705 , G01R31/31721 , G01R31/31723 , G01R31/3177 , G06F11/36 , G06F11/3648
摘要： An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.
摘要翻译： 一种集成电路芯片装置，包括：系统电路; 调试电路被配置为调试系统电路，调试电路被分段成区域; 其中所述调试电路包括被配置为将调试消息通过区域从所述互连结构的区域入口节点路由到所述互连结构的区域出口节点的互连结构; 并且其中所述调试电路被配置为在接收到比指定长度短的区域入口节点处的调试消息时，通过将所述调试消息的长度增加到所述指定长度来修改所述调试消息以形成修改的调试消息。
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公开(公告)号：US09140753B2
公开(公告)日：2015-09-22
申请号：US14251157
申请日：2014-04-11
IPC分类号： G06F11/26 , G01R31/3177 , G01R31/317 , G06F11/36
CPC分类号： G01R31/3177 , G01R31/31705 , G06F11/3648
摘要： A method of validating functional testing of system circuitry on an integrated circuit chip, the system circuitry configured to perform a plurality of functions, the integrated circuit chip further comprising debugging circuitry under the control of a debug controller, the debugging circuitry comprising at least one debug unit. The method comprises: at the system circuitry, performing one of the plurality of functions; applying a debug configuration to the at least one debug unit; and at the at least one debug unit, monitoring for a characteristic in the system circuitry's performance of the one of the plurality of functions according to that debug configuration, and reporting to the debug controller.
摘要翻译： 一种验证集成电路芯片上的系统电路的功能测试的方法，所述系统电路被配置为执行多个功能，所述集成电路芯片还包括在调试控制器的控制下的调试电路，所述调试电路包括至少一个调试 单元。 该方法包括：在系统电路处执行多个功能之一; 将调试配置应用于所述至少一个调试单元; 以及在所述至少一个调试单元处，根据所述调试配置来监视所述系统电路中的所述多个功能中的一个的性能的特征，以及向所述调试控制器报告。
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公开(公告)号：US20150226801A1
公开(公告)日：2015-08-13
申请号：US14251044
申请日：2014-04-11
IPC分类号： G01R31/317 , G01R31/3177
CPC分类号： G01R31/31705 , G01R31/31725 , G01R31/31727 , G01R31/3177
摘要： A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.
摘要翻译： 一种在集成电路芯片上功能测试系统电路的方法，所述系统电路包括多个子电路，并且所述集成电路芯片还包括调试电路，所述调试电路包括可变电路。 该方法包括：在系统电路处，执行由执行并发动作的子电路的功能; 在可变性电路中，改变并行动作的相对定时，以增加系统电路的功能性能中的一个或多个错误的可能性; 并且在调试电路中，记录系统电路的功能性能中的一个或多个错误。
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28.发明授权Data processing apparatus and related methods of debugging processing circuitry 有权调试处理电路的数据处理装置及相关方法公开(公告)号：US08826081B2
公开(公告)日：2014-09-02
申请号：US13690923
申请日：2012-11-30
IPC分类号： G06F11/273 , G06F11/36
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A data processing apparatus having processing circuitry and debug circuitry is debugged by operating the processing circuitry to generate data. The debug circuitry is employed to generate trace elements indicative of the operation of the processing circuitry. Trace elements are caused to be output from the data processing apparatus over a communication bus capable of connecting a plurality of devices. The communication bus is controlled by a protocol for data interchange requiring data interchange from any device on the communication bus to be controlled by a single processing system. The passing of the trace elements onto the communication bus is controlled using an interface unit of the debug circuitry. The interface unit comprises a controller arranged to allow each of the interface unit and processing circuitry to be separate processing systems which can each independently control data interchange from the data processing apparatus.
摘要翻译： 具有处理电路和调试电路的数据处理装置通过操作处理电路来产生数据进行调试。 调试电路用于产生指示处理电路的操作的迹线元件。 使得能够通过能够连接多个设备的通信总线从数据处理设备输出跟踪元件。 通信总线由用于数据交换的协议控制，需要从通信总线上的任何设备进行数据交换以由单个处理系统控制。 使用调试电路的接口单元来控制将微量元件传递到通信总线上。 接口单元包括控制器，其布置成允许接口单元和处理电路中的每一个是分别的处理系统，其可以独立地控制数据交换从数据处理设备。
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公开(公告)号：US20140013172A1
公开(公告)日：2014-01-09
申请号：US13938088
申请日：2013-07-09
IPC分类号： G01R31/317
CPC分类号： G01R31/31705 , G06F11/3656
摘要： Roughly described, a method of controlling transportation of debug data on an integrated circuit chip, the integrated circuit chip comprising a shared hub and a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, wherein between each respective debug unit and the shared hub there is an interface configured to transport data messages over each of a plurality of flows, the flows being assigned priorities, the method comprising: transporting control data for controlling the state of a debug unit on a priority flow having a first priority; and transporting debug data output by a debug unit as a result of debugging the peripheral circuit connected to that debug unit on a flow having a second priority, wherein the first priority is higher than the second priority.
摘要翻译： 粗略地描述了一种控制集成电路芯片上的调试数据传输的方法，该集成电路芯片包括共享集线器和多个外围电路，每个外围电路连接到相应的调试单元，其中在各个调试单元和 所述共享集线器具有被配置为在多个流中的每一个上传送数据消息的接口，所述流被分配优先级，所述方法包括：传送控制数据，用于控制具有第一优先级的优先级流的调试单元的状态; 以及传送由调试单元输出的调试数据，其结果是对具有第二优先级的流调试连接到该调试单元的外围电路，其中第一优先级高于第二优先级。
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公开(公告)号：US20140013161A1
公开(公告)日：2014-01-09
申请号：US13938065
申请日：2013-07-09
IPC分类号： G06F11/263
CPC分类号： G06F11/263 , G06F11/267
摘要： Roughly described, a method of sending a message from a source unit to a destination unit both forming part of a hierarchical debug architecture on a chip, the units in the hierarchy using a protocol in which each unit has an internal address which is the same base address, and in which each unit addresses other units using addresses derivable relative to that unit's internal address given positions of other units in the hierarchy, comprising: the source unit in a first level of the hierarchy sending a message comprising a destination address of the destination unit, the destination address being relative to the source unit's internal address, and an intermediate unit in a second level of the hierarchy: adding an offset to the destination address to form a rebased destination address, being relative to the intermediate unit's internal address, and routing the rebased message onto the destination unit.
摘要翻译： 粗略地描述了一种从源单元向目的地单元发送消息的方法，它们都构成了芯片上分层调试架构的一部分，层级中的单元使用其中每个单元具有相同基址的内部地址的协议 地址，并且其中每个单元使用可以相对于该单元的内部地址导出的其他单元寻址给定层级中的其他单元的位置，其包括：层级的第一级中的源单元发送包括目的地的目的地地址的消息 单元，目的地地址相对于源单元的内部地址，以及在层次结构的第二级中的中间单元：向目的地地址添加偏移量以形成相对于中间单元的内部地址的重定位的目的地地址，以及 将重新封装的消息路由到目标单元。
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