公开(公告)号：US07602875B2

公开(公告)日：2009-10-13

申请号：US11041239

申请日：2005-01-25

申请人： Eiji Sudo ,  Yasushi Ooi

发明人： Eiji Sudo ,  Yasushi Ooi

IPC分类号： H04L25/40 ,  H04L23/00

CPC分类号： H03H17/0628 ,  H03H17/0219

摘要： A sampling apparatus for converting first data, sampled at a first sampling rate, into second data, sampled at a second sampling rate. A FIFO storing the first data based on a write control signal and outputs the second data read out based on a read control signal indicating whether the second data is to be read out during the next time interval. The apparatus further includes a frequency detection unit for measuring the first clock signal during the current time interval to generate the value of the first current clock frequency, generating the value of a current predicted clock frequency from the value of the first current clock frequency and the value of the directly previously predicted clock frequency and for using the value of the current predicted clock frequency as the directly previously predicted clock frequency during the next time interval. A calculating unit generates the write control signal and read control signal from the value of a second current frequency, generated by measuring the second clock signal during the current time interval, to output the write and read control signal to the FIFO.

摘要翻译： 一种采样装置，用于将以第一采样率采样的第一数据转换成以第二采样率采样的第二数据。 一种FIFO，其基于写控制信号存储第一数据，并且基于指示在下一时间间隔期间是否读出第二数据的读控制信号输出读出的第二数据。 该装置还包括频率检测单元，用于在当前时间间隔期间测量第一时钟信号以产生第一当前时钟频率的值，从第一当前时钟频率的值产生当前预测时钟频率的值，并且 并且使用当前预测时钟频率的值作为在下一时间间隔期间直接预先预测的时钟频率的值。 计算单元从当前时间间隔内测量第二时钟信号产生的第二当前频率值产生写入控制信号和读取控制信号，以将写和读控制信号输出到FIFO。

公开(公告)号：US20090163159A1

公开(公告)日：2009-06-25

申请号：US12314831

申请日：2008-12-17

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H03D7/16

CPC分类号： H03D3/008 ,  H03J1/005

摘要： A radio receiver includes a frequency converter, an oscillation circuit, an A/D converter, and a digital demodulator. The A/D converter digitally samples the intermediate frequency signal by using one of an oscillating frequency, a multiplying frequency, and a dividing frequency of the clock signal as a sampling frequency. The digital demodulator performs a digital demodulation processing by using the intermediate frequency signal digitally sampled and by using the one of the oscillating frequency, the multiplying frequency, and the dividing frequency of the clock signal as an operating frequency. The oscillating frequency is within a predetermined range. The predetermined range is at least one of equal to or more than 37.1 MHz and less than or equal to 37.9 MHz, equal to or more than 54.1 MHz and less than or equal to 64.8 MHz, and equal to or more than 74.2 MHz and less than or equal to 75.8 MHz.

摘要翻译： 无线电接收机包括频率转换器，振荡电路，A / D转换器和数字解调器。 A / D转换器通过使用振荡频率，乘法频率和时钟信号的除频率之一作为采样频率对中频信号进行数字采样。 数字解调器通过使用数字采样的中频信号和通过使用时钟信号的振荡频率，乘法频率和分频频率中的一个作为工作频率来执行数字解调处理。 振荡频率在预定范围内。 预定范围是等于或大于37.1MHz且小于或等于37.9MHz，等于或大于54.1MHz且小于或等于64.8MHz，等于或大于74.2MHz和更小的至少一个 大于或等于75.8MHz。

公开(公告)号：US06249550B1

公开(公告)日：2001-06-19

申请号：US08931650

申请日：1997-09-16

申请人： Masayuki Mizuno ,  Yasushi Ooi

发明人： Masayuki Mizuno ,  Yasushi Ooi

IPC分类号： H04N712

CPC分类号： H04N5/145 ,  G06T7/223 ,  G06T7/238 ,  G06T2207/10016 ,  H04N19/51 ,  H04N19/56

摘要： In a motion vector estimating apparatus, a current picture storage unit stores image data of a current picture, and a reference picture storage unit stores image data of a reference picture. A search window determining unit determines estimation history from previously estimated motion vectors, and determines a search window based on the estimation history. At least one of a shape, size and position of the search window is determined based on the estimation history. The search window is composed of rectangular reference regions. A block matching circuit for performing a block matching process to a current block and each of reference blocks of the search window to determine a motion vector. The search window may be limited in units of pixels, or a load of the apparatus, a power supply voltage or a temperature of the block matching circuit.

摘要翻译： 在运动矢量估计装置中，当前图像存储单元存储当前图像的图像数据，参考图像存储单元存储参考图像的图像数据。 搜索窗口确定单元从先前估计的运动矢量确定估计历史，并且基于估计历史来确定搜索窗口。 基于估计历史来确定搜索窗口的形状，大小和位置中的至少一个。 搜索窗口由矩形参考区域组成。 一种块匹配电路，用于对当前块和搜索窗口的每个参考块执行块匹配处理以确定运动矢量。 搜索窗口可以以像素的单位，装置的负载，电源电压或块匹配电路的温度来限制。

公开(公告)号：US5347636A

公开(公告)日：1994-09-13

申请号：US965534

申请日：1992-10-23

申请人： Yasushi Ooi ,  Yoshiyuki Miki

发明人： Yasushi Ooi ,  Yoshiyuki Miki

IPC分类号： G06F12/10 ,  G06F15/00

CPC分类号： G06F12/1027 ,  G06F2212/206

摘要： A data processor which includes at least a central processing unit adapted to execute virtual memory management. The central processing unit internally includes a translation lookaside buffer (TLB) for translating a given virtual address into a corresponding real address. The TLB also generates a distinction signal indicating whether the translated real address designates a main memory or an external input/output device. In response to the distinction signal, a control signal generator outputs a set of input/output control signals for the access of the type designated by the distinction signal.

摘要翻译： 一种数据处理器，其至少包括适于执行虚拟存储器管理的中央处理单元。 中央处理单元内部包括用于将给定虚拟地址转换为对应的实际地址的翻译后备缓冲器（TLB）。 TLB还产生指示翻译的真实地址是指定主存储器还是外部输入/输出设备的区分信号。 响应于区分信号，控制信号发生器输出一组输入/输出控制信号，用于访问由区别信号指定的类型。

公开(公告)号：US5239660A

公开(公告)日：1993-08-24

申请号：US784509

申请日：1991-10-30

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： G06F9/38 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8076

摘要： In a vector calculation unit (31), a multiplication and an addition result register (50 and 53) are connected to a pipeline multiplier (14) and a pipeline adder (15), respectively. A multiplication and an addition result bus (52 and 55) are connected to the multiplication and the addition result registers, respectively. A selector (S1) connects one of an input bus (11) and the multiplication and the addition result buses to the first operand register to which a first multiplication and a first addition operand bus (44 and 45') are connected. A selector (S2) connects one of another input bus (12) and the multiplication and the addition result buses to the second operand register to which second multiplication and second addition operand buses (48 and 49) are connected. A selector (S3) connects one of the first multiplication operand, the multiplication result, and the addition result buses to an input of the multiplier. A selector (S4) connects one of the second multiplication operand, the multiplication result, and the addition result buses to another input of the multiplier. A selector (S5) connects one of the first addition operand, the multiplication result, and the addition result buses to an input of the adder. A selector (S6) connects one of the second addition operand, the multiplication result, and the addition result buses to another input of the adder. A selector (S7) connects one of the first addition operand, the second addition operand, the multiplication result, and the addition result buses to an output bus (13).