公开(公告)号：US20080013617A1

公开(公告)日：2008-01-17

申请号：US11826185

申请日：2007-07-12

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H04L27/01

CPC分类号： H04B1/1027 ,  H04L25/0305 ,  H04L2025/03394 ,  H04L2025/03401 ,  H04L2025/0363 ,  H04L2025/03707

摘要： An adaptive equalizer according to an embodiment of the present invention includes: an adaptive filter; and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal modulated by a modulation method that produces a demodulated signal with constant amplitude characteristics so as to make an amplitude of an equalized output signal constant. The control unit controls stop and execution of the adaptive equalization processing of the adaptive filter in accordance with characteristics of at least one of the input signal and the output signal.

摘要翻译： 根据本发明实施例的自适应均衡器包括：自适应滤波器; 和控制单元。 自适应滤波器对通过产生具有恒定幅度特性的解调信号的调制方法调制的输入信号进行自适应均衡处理，以使均衡输出信号的幅度恒定。 控制单元根据输入信号和输出信号中的至少一个的特性控制自适应滤波器的自适应均衡处理的停止和执行。

公开(公告)号：US06366616B1

公开(公告)日：2002-04-02

申请号：US09652135

申请日：2000-08-31

申请人： Masayuki Mizuno ,  Yasushi Ooi

发明人： Masayuki Mizuno ,  Yasushi Ooi

IPC分类号： H04N712

CPC分类号： H04N5/145 ,  G06T7/223 ,  G06T7/238 ,  G06T2207/10016 ,  H04N19/51 ,  H04N19/56

摘要： In a motion vector estimating apparatus, a current picture storage unit stores image data of a current picture, and a reference-picture storage unit stores image data of a reference picture. A search window determining unit determines estimation history from previously estimated motion vectors, and determines a search window based on the estimation history. At least one of a shape, size and position of the search window is determined based on the estimation history. The search window is composed of rectangular reference regions. A block matching circuit for performing a block matching process to a current block and each of reference blocks of the search window to determine a motion vector. The search window may be limited in units of pixels, or a load of the apparatus, a power supply voltage or a temperature of the block matching circuit.

摘要翻译： 在运动矢量估计装置中，当前图像存储单元存储当前图像的图像数据，并且参考图像存储单元存储参考图像的图像数据。 搜索窗口确定单元从先前估计的运动矢量确定估计历史，并且基于估计历史来确定搜索窗口。 基于估计历史来确定搜索窗口的形状，大小和位置中的至少一个。 搜索窗口由矩形参考区域组成。 一种块匹配电路，用于对当前块和搜索窗口的每个参考块执行块匹配处理以确定运动矢量。 搜索窗口可以以像素的单位，装置的负载，电源电压或块匹配电路的温度来限制。

公开(公告)号：US5903674A

公开(公告)日：1999-05-11

申请号：US939169

申请日：1997-09-29

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H04N19/50 ,  G06T1/20 ,  G06T9/00 ,  H03M7/30 ,  H04N5/14 ,  H04N19/103 ,  H04N19/126 ,  H04N19/13 ,  H04N19/136 ,  H04N19/137 ,  H04N19/14 ,  H04N19/147 ,  H04N19/174 ,  H04N19/176 ,  H04N19/196 ,  H04N19/42 ,  H04N19/423 ,  H04N19/46 ,  H04N19/503 ,  H04N19/567 ,  H04N19/57 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/85 ,  H04N19/87 ,  H04N19/91 ,  G06K9/00

CPC分类号： H04N19/42 ,  H04N19/61 ,  H04N5/145

摘要： Video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 are coupled with frame memory 10 through buffer and frame memory controlling portion 9 and controlling processor 1 through host interface portion 2. Frame memory 10 is accessed by video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 in time sharing manner. Controlling of video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 is centralized in controlling processor 1. Portions in dotted frame 20 are integrated in one LSI chip.

摘要翻译： 视频输入部分3，视频输出部分8，运动估计部分4，像素级运算部分5，可变长度编码部分6和代码输出部分7通过缓冲器和帧与帧存储器10耦合 存储器控制部分9和控制处理器1通过主机接口部分2.帧存储器10由视频输入部分3，视频输出部分8，运动估计部分4，像素级算术部分5，可变长度 - 编码部分6和代码输出部分7。 视频输入部分3，视频输出部分8，运动估计部分4，像素级算术部分5，可变长度编码部分6和代码输出部分7的控制集中在控制处理器1中。部分 点阵框架20集成在一个LSI芯片中。

公开(公告)号：US5589885A

公开(公告)日：1996-12-31

申请号：US400499

申请日：1995-03-08

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H04N19/50 ,  G06T9/00 ,  H04N19/42 ,  H04N19/423 ,  H04N19/503 ,  H04N19/51 ,  H04N19/577 ,  H04N19/61 ,  H04N19/625 ,  H04N19/85 ,  H04N19/91 ,  H04N19/93 ,  H04N7/32

CPC分类号： H04N19/42 ,  H04N19/61

摘要： A moving picture coding and decoding circuit which can cope with a plurality of algorithms to reduce the number of components and facilitate extension. A picture to be coded is inputted to a motion detection/prediction section, which outputs a predictive difference signal and a predictive signal. DCT processing and quantization are performed for the predictive difference signal by a conversion coding and decoding section, from which a conversion coefficient signal is outputted to an interface bus. The conversion coding and decoding section also executes dequantization and inverse DCT processing of the conversion coefficient, adds the predictive signal to the conversion coefficient and outputs a result of the picture coding to an image data bus. A programmable architecture as in a digital signal processor is applied to the conversion coding and decoding section. The conversion coefficient outputted from the conversion coding and decoding section is stored into a FIFO memory of a zigzag scan/entropy coding section and then undergoes coding in an entropy coding section. A bit stream thus coded is stored once into and then outputted as codes from another FIFO memory.

摘要翻译： 一种运动图像编码和解码电路，可以应对多种算法，以减少部件的数量并促进扩展。 要编码的图像被输入到运动检测/预测部分，其输出预测差分信号和预测信号。 通过转换编码和解码部分对预测差分信号进行DCT处理和量化，转换系数信号从该转换编码和解码部分输出到接口总线。 转换编码和解码部分还执行转换系数的逆量化和逆DCT处理，将预测信号与转换系数相加，并将图像编码的结果输出到图像数据总线。 在数字信号处理器中的可编程架构被应用于转换编码和解码部分。 从转换编码解码部输出的转换系数存储在Z字形扫描/熵编码部的FIFO存储器中，然后在熵编码部中进行编码。 这样编码的比特流被存储一次，然后作为来自另一个FIFO存储器的代码被输出。

公开(公告)号：US5553257A

公开(公告)日：1996-09-03

申请号：US189680

申请日：1994-02-01

申请人： Hideo Ishida ,  Yasushi Ooi

发明人： Hideo Ishida ,  Yasushi Ooi

IPC分类号： H03M7/42 ,  H04N7/26 ,  H04N7/30 ,  G06F12/00

CPC分类号： H03M7/42 ,  H04N19/13 ,  H04N19/60 ,  H04N19/91

摘要： An address generating circuit having a two-dimensional coding table which has respective coded words corresponding to a combination of x and y where the value of event A is determined as x and the value of event B as y (x and y are positive integers) between two events A and B, and stores the coded words in an address corresponding to each combination of x and y; coincidence detectors which input the values x and y of the events A and B and detect whether these values coincide with the integer of 1 to S (S is the maximum number among the integers satisfying S+log.sub.2 S

摘要翻译： 具有二维编码表的地址生成电路，其具有对应于事件A的值被确定为x的事件A的值和事件B的值对应于x和y的组合的各个编码字，y（x和y是正整数） 在两个事件A和B之间，并且将编码的字存储在与x和y的每个组合相对应的地址中; 输入事件A和B的值x和y并检测这些值是否与1到S的整数一致的符合检测器（S是满足S + log2S

公开(公告)号：US5375238A

公开(公告)日：1994-12-20

申请号：US796261

申请日：1991-11-20

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： G06F9/32 ,  G06F9/34 ,  G06F9/40 ,  G06F9/30

CPC分类号： G06F9/325

摘要： A nesting management mechanism for use in a loop controlling system, comprises a program counter coupled to a program counter bus and incremented each time one instruction is executed, and a loop counter coupled with the program counter bus and set with the number of loops to be executed when a loop execution is executed. The loop counter is decremented each time one loop is completed. A loop start address register is coupled to the program counter bus and set with a loop start address when the loop execution is executed, and a loop end address register is coupled to the program counter bus and set with a loop end address when the loop execution is executed. First, second and third independent hardware stacks of a first-in last-out type are provided for the loop counter, the loop start address register, and the loop end address register, respectively, so as to save respective contents of the loop counter, the loop start address register, and the loop end address register at the time of a loop nesting.

摘要翻译： 一种在循环控制系统中使用的嵌套管理机制，包括耦合到程序计数器总线的程序计数器，并且每次执行一个指令时递增，以及循环计数器与程序计数器总线耦合，并将循环数设置为 执行循环执行时执行。 每次循环结束时，循环计数器递减。 循环起始地址寄存器耦合到程序计数器总线，并在执行循环执行时设置循环起始地址，循环结束地址寄存器耦合到程序计数器总线，并在循环执行时设置循环结束地址 被执行。 分别为循环计数器，循环起始地址寄存器和循环结束地址寄存器分别提供了先入先出类型的第一，第二和第三独立硬件堆栈，以便保存循环计数器的各个内容， 循环起始地址寄存器和循环结束地址寄存器。

公开(公告)号：US5226129A

公开(公告)日：1993-07-06

申请号：US754314

申请日：1991-09-04

申请人： Yasushi Ooi ,  Yoshikuni Sato

发明人： Yasushi Ooi ,  Yoshikuni Sato

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/355

CPC分类号： G06F9/355 ,  G06F9/30149 ,  G06F9/321 ,  G06F9/3557

摘要： A processor capable of processing a variable word length instruction has a program counter controlled to indicate the head of an instruction by the value of the program counter. There are provided an adder for summing the length of decoded portions in the variable word length instruction in accordance with the progress of the instruction decoding, and another adder for adding the length of the decoded instruction portions to the program counter so as to update the program counter. Further, there is provided a circuit for calculating an operand effective address by using the value of the program counter in the course of the variable word length instruction decoding. Thus, the updating of the program counter and the generation of the effective address are concurrently executed.

摘要翻译： 能够处理可变字长度指令的处理器具有控制程序计数器，以通过程序计数器的值指示指令的头部。 提供了一种加法器，用于根据指令解码的进程对可变字长度指令中的解码部分的长度进行求和，以及用于将解码的指令部分的长度与程序计数器相加的另一加法器，以便更新程序 计数器。 此外，提供了一种用于在可变字长指令解码过程中通过使用程序计数器的值来计算操作数有效地址的电路。 因此，同时执行程序计数器的更新和有效地址的生成。

公开(公告)号：US08259785B2

公开(公告)日：2012-09-04

申请号：US11826185

申请日：2007-07-12

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H03K5/159

CPC分类号： H04B1/1027 ,  H04L25/0305 ,  H04L2025/03394 ,  H04L2025/03401 ,  H04L2025/0363 ,  H04L2025/03707

摘要： An adaptive equalizer includes: an adaptive filter; and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal modulated by a modulation method that produces a modulation signal with constant amplitude characteristics so as to make an amplitude of an equalized output signal constant. The control unit controls stop and execution of the adaptive equalization processing of the adaptive filter in accordance with characteristics of at least one of the input signal and the output signal.

摘要翻译： 自适应均衡器包括：自适应滤波器; 和控制单元。 自适应滤波器对由产生具有恒定幅度特性的调制信号的调制方法调制的输入信号执行自适应均衡处理，以使均衡输出信号的幅度恒定。 控制单元根据输入信号和输出信号中的至少一个的特性控制自适应滤波器的自适应均衡处理的停止和执行。

公开(公告)号：US20090190646A1

公开(公告)日：2009-07-30

申请号：US12318642

申请日：2009-01-05

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H03H7/30 ,  H03K5/159

CPC分类号： H04L25/03057 ,  H04L2025/03681

摘要： An adaptive equalizer includes an adaptive filter and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal so as to make an amplitude of an equalized output signal constant, the input signal being modulated by a modulation system that produces a modulation signal with constant amplitude characteristics. The control unit gradually changes equalization ability of the adaptive equalization processing of the adaptive filter in accordance with characteristics of the input signal.

摘要翻译： 自适应均衡器包括自适应滤波器和控制单元。 自适应滤波器对输入信号执行自适应均衡处理，以使均衡输出信号的幅度恒定，输入信号由产生具有恒定幅度特性的调制信号的调制系统调制。 控制单元根据输入信号的特性逐渐改变自适应滤波器的自适应均衡处理的均衡能力。

公开(公告)号：US20050163276A1

公开(公告)日：2005-07-28

申请号：US11041239

申请日：2005-01-25

申请人： Eiji Sudo ,  Yasushi Ooi

发明人： Eiji Sudo ,  Yasushi Ooi

IPC分类号： H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  H04B1/38 ,  H04B14/04

CPC分类号： H03H17/0628 ,  H03H17/0219

摘要： Disclosed is a sampling rate conversion apparatus for converting first data, sampled at a first sampling rate, into second data, sampled at a second sampling rate, includes a FIFO for storing the first data responsive to a first clock signal and for outputting the first data as second data responsive to the second clock signal. This FIFO stores the first data based on a write control signal indicating whether or not the first data written directly previously is to be updated to the first data, and outputs the second data read out based on a read control signal indicating whether or not the second data as read out is to be read out during the next time interval as well. The sampling rate conversion apparatus also includes a frequency detection unit for measuring the first clock signal during the current time interval to generate the value of the first current clock frequency, generating the value of a current predicted clock frequency from the value of the first current clock frequency and the value of the directly previously predicted clock frequency and for using the value of the current predicted clock frequency as the directly previously predicted clock frequency during the next time interval, and a calculating unit supplied with the first data to output the data to the FIFO. The calculating unit generates write control signal and read control signal from the value of a second current frequency, generated by measuring the second clock signal during the current time interval, and from the value of the current predicted clock frequency, to output the so generated write and read control signal to the FIFO.

摘要翻译： 公开了一种用于将以第一采样率采样的第一数据转换为以第二采样率采样的第二数据的采样率转换装置，包括用于响应于第一时钟信号存储第一数据并用于输出第一数据的FIFO 作为响应于第二时钟信号的第二数据。 该FIFO基于写入控制信号存储第一数据，该写入控制信号指示先前直接写入的第一数据是否被更新为第一数据，并且基于读取控制信号输出第二数据，该读取控制信号指示是否第二个 读出的数据也将在下一个时间间隔期间读出。 采样率转换装置还包括频率检测单元，用于在当前时间间隔期间测量第一时钟信号以产生第一当前时钟频率的值，从第一当前时钟的值产生当前预测时钟频率的值 频率和直接预先预测的时钟频率的值，并且使用当前预测时钟频率的值作为在下一时间间隔期间的直接预测的时钟频率，以及计算单元，被提供有第一数据以将数据输出到 FIFO。 计算单元根据当前时间间隔内的第二时钟信号的测量值和从当前预测时钟频率的值产生的第二当前频率的值来生成写控制信号和读控制信号，以输出所生成的写 并读取FIFO的控制信号。