公开(公告)号：US06249550B1

公开(公告)日：2001-06-19

申请号：US08931650

申请日：1997-09-16

申请人： Masayuki Mizuno ,  Yasushi Ooi

发明人： Masayuki Mizuno ,  Yasushi Ooi

IPC分类号： H04N712

CPC分类号： H04N5/145 ,  G06T7/223 ,  G06T7/238 ,  G06T2207/10016 ,  H04N19/51 ,  H04N19/56

摘要： In a motion vector estimating apparatus, a current picture storage unit stores image data of a current picture, and a reference picture storage unit stores image data of a reference picture. A search window determining unit determines estimation history from previously estimated motion vectors, and determines a search window based on the estimation history. At least one of a shape, size and position of the search window is determined based on the estimation history. The search window is composed of rectangular reference regions. A block matching circuit for performing a block matching process to a current block and each of reference blocks of the search window to determine a motion vector. The search window may be limited in units of pixels, or a load of the apparatus, a power supply voltage or a temperature of the block matching circuit.

摘要翻译： 在运动矢量估计装置中，当前图像存储单元存储当前图像的图像数据，参考图像存储单元存储参考图像的图像数据。 搜索窗口确定单元从先前估计的运动矢量确定估计历史，并且基于估计历史来确定搜索窗口。 基于估计历史来确定搜索窗口的形状，大小和位置中的至少一个。 搜索窗口由矩形参考区域组成。 一种块匹配电路，用于对当前块和搜索窗口的每个参考块执行块匹配处理以确定运动矢量。 搜索窗口可以以像素的单位，装置的负载，电源电压或块匹配电路的温度来限制。

公开(公告)号：US06366616B1

公开(公告)日：2002-04-02

申请号：US09652135

申请日：2000-08-31

申请人： Masayuki Mizuno ,  Yasushi Ooi

发明人： Masayuki Mizuno ,  Yasushi Ooi

IPC分类号： H04N712

CPC分类号： H04N5/145 ,  G06T7/223 ,  G06T7/238 ,  G06T2207/10016 ,  H04N19/51 ,  H04N19/56

摘要： In a motion vector estimating apparatus, a current picture storage unit stores image data of a current picture, and a reference-picture storage unit stores image data of a reference picture. A search window determining unit determines estimation history from previously estimated motion vectors, and determines a search window based on the estimation history. At least one of a shape, size and position of the search window is determined based on the estimation history. The search window is composed of rectangular reference regions. A block matching circuit for performing a block matching process to a current block and each of reference blocks of the search window to determine a motion vector. The search window may be limited in units of pixels, or a load of the apparatus, a power supply voltage or a temperature of the block matching circuit.

摘要翻译： 在运动矢量估计装置中，当前图像存储单元存储当前图像的图像数据，并且参考图像存储单元存储参考图像的图像数据。 搜索窗口确定单元从先前估计的运动矢量确定估计历史，并且基于估计历史来确定搜索窗口。 基于估计历史来确定搜索窗口的形状，大小和位置中的至少一个。 搜索窗口由矩形参考区域组成。 一种块匹配电路，用于对当前块和搜索窗口的每个参考块执行块匹配处理以确定运动矢量。 搜索窗口可以以像素的单位，装置的负载，电源电压或块匹配电路的温度来限制。

公开(公告)号：US20080013617A1

公开(公告)日：2008-01-17

申请号：US11826185

申请日：2007-07-12

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H04L27/01

CPC分类号： H04B1/1027 ,  H04L25/0305 ,  H04L2025/03394 ,  H04L2025/03401 ,  H04L2025/0363 ,  H04L2025/03707

摘要： An adaptive equalizer according to an embodiment of the present invention includes: an adaptive filter; and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal modulated by a modulation method that produces a demodulated signal with constant amplitude characteristics so as to make an amplitude of an equalized output signal constant. The control unit controls stop and execution of the adaptive equalization processing of the adaptive filter in accordance with characteristics of at least one of the input signal and the output signal.

摘要翻译： 根据本发明实施例的自适应均衡器包括：自适应滤波器; 和控制单元。 自适应滤波器对通过产生具有恒定幅度特性的解调信号的调制方法调制的输入信号进行自适应均衡处理，以使均衡输出信号的幅度恒定。 控制单元根据输入信号和输出信号中的至少一个的特性控制自适应滤波器的自适应均衡处理的停止和执行。

公开(公告)号：US07602875B2

公开(公告)日：2009-10-13

申请号：US11041239

申请日：2005-01-25

申请人： Eiji Sudo ,  Yasushi Ooi

发明人： Eiji Sudo ,  Yasushi Ooi

IPC分类号： H04L25/40 ,  H04L23/00

CPC分类号： H03H17/0628 ,  H03H17/0219

摘要： A sampling apparatus for converting first data, sampled at a first sampling rate, into second data, sampled at a second sampling rate. A FIFO storing the first data based on a write control signal and outputs the second data read out based on a read control signal indicating whether the second data is to be read out during the next time interval. The apparatus further includes a frequency detection unit for measuring the first clock signal during the current time interval to generate the value of the first current clock frequency, generating the value of a current predicted clock frequency from the value of the first current clock frequency and the value of the directly previously predicted clock frequency and for using the value of the current predicted clock frequency as the directly previously predicted clock frequency during the next time interval. A calculating unit generates the write control signal and read control signal from the value of a second current frequency, generated by measuring the second clock signal during the current time interval, to output the write and read control signal to the FIFO.

摘要翻译： 一种采样装置，用于将以第一采样率采样的第一数据转换成以第二采样率采样的第二数据。 一种FIFO，其基于写控制信号存储第一数据，并且基于指示在下一时间间隔期间是否读出第二数据的读控制信号输出读出的第二数据。 该装置还包括频率检测单元，用于在当前时间间隔期间测量第一时钟信号以产生第一当前时钟频率的值，从第一当前时钟频率的值产生当前预测时钟频率的值，并且 并且使用当前预测时钟频率的值作为在下一时间间隔期间直接预先预测的时钟频率的值。 计算单元从当前时间间隔内测量第二时钟信号产生的第二当前频率值产生写入控制信号和读取控制信号，以将写和读控制信号输出到FIFO。

公开(公告)号：US20090163159A1

公开(公告)日：2009-06-25

申请号：US12314831

申请日：2008-12-17

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H03D7/16

CPC分类号： H03D3/008 ,  H03J1/005

摘要： A radio receiver includes a frequency converter, an oscillation circuit, an A/D converter, and a digital demodulator. The A/D converter digitally samples the intermediate frequency signal by using one of an oscillating frequency, a multiplying frequency, and a dividing frequency of the clock signal as a sampling frequency. The digital demodulator performs a digital demodulation processing by using the intermediate frequency signal digitally sampled and by using the one of the oscillating frequency, the multiplying frequency, and the dividing frequency of the clock signal as an operating frequency. The oscillating frequency is within a predetermined range. The predetermined range is at least one of equal to or more than 37.1 MHz and less than or equal to 37.9 MHz, equal to or more than 54.1 MHz and less than or equal to 64.8 MHz, and equal to or more than 74.2 MHz and less than or equal to 75.8 MHz.

摘要翻译： 无线电接收机包括频率转换器，振荡电路，A / D转换器和数字解调器。 A / D转换器通过使用振荡频率，乘法频率和时钟信号的除频率之一作为采样频率对中频信号进行数字采样。 数字解调器通过使用数字采样的中频信号和通过使用时钟信号的振荡频率，乘法频率和分频频率中的一个作为工作频率来执行数字解调处理。 振荡频率在预定范围内。 预定范围是等于或大于37.1MHz且小于或等于37.9MHz，等于或大于54.1MHz且小于或等于64.8MHz，等于或大于74.2MHz和更小的至少一个 大于或等于75.8MHz。

公开(公告)号：US5347636A

公开(公告)日：1994-09-13

申请号：US965534

申请日：1992-10-23

申请人： Yasushi Ooi ,  Yoshiyuki Miki

发明人： Yasushi Ooi ,  Yoshiyuki Miki

IPC分类号： G06F12/10 ,  G06F15/00

CPC分类号： G06F12/1027 ,  G06F2212/206

摘要： A data processor which includes at least a central processing unit adapted to execute virtual memory management. The central processing unit internally includes a translation lookaside buffer (TLB) for translating a given virtual address into a corresponding real address. The TLB also generates a distinction signal indicating whether the translated real address designates a main memory or an external input/output device. In response to the distinction signal, a control signal generator outputs a set of input/output control signals for the access of the type designated by the distinction signal.

摘要翻译： 一种数据处理器，其至少包括适于执行虚拟存储器管理的中央处理单元。 中央处理单元内部包括用于将给定虚拟地址转换为对应的实际地址的翻译后备缓冲器（TLB）。 TLB还产生指示翻译的真实地址是指定主存储器还是外部输入/输出设备的区分信号。 响应于区分信号，控制信号发生器输出一组输入/输出控制信号，用于访问由区别信号指定的类型。

公开(公告)号：US5239660A

公开(公告)日：1993-08-24

申请号：US784509

申请日：1991-10-30

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： G06F9/38 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8076

摘要： In a vector calculation unit (31), a multiplication and an addition result register (50 and 53) are connected to a pipeline multiplier (14) and a pipeline adder (15), respectively. A multiplication and an addition result bus (52 and 55) are connected to the multiplication and the addition result registers, respectively. A selector (S1) connects one of an input bus (11) and the multiplication and the addition result buses to the first operand register to which a first multiplication and a first addition operand bus (44 and 45') are connected. A selector (S2) connects one of another input bus (12) and the multiplication and the addition result buses to the second operand register to which second multiplication and second addition operand buses (48 and 49) are connected. A selector (S3) connects one of the first multiplication operand, the multiplication result, and the addition result buses to an input of the multiplier. A selector (S4) connects one of the second multiplication operand, the multiplication result, and the addition result buses to another input of the multiplier. A selector (S5) connects one of the first addition operand, the multiplication result, and the addition result buses to an input of the adder. A selector (S6) connects one of the second addition operand, the multiplication result, and the addition result buses to another input of the adder. A selector (S7) connects one of the first addition operand, the second addition operand, the multiplication result, and the addition result buses to an output bus (13).

公开(公告)号：US5903674A

公开(公告)日：1999-05-11

申请号：US939169

申请日：1997-09-29

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H04N19/50 ,  G06T1/20 ,  G06T9/00 ,  H03M7/30 ,  H04N5/14 ,  H04N19/103 ,  H04N19/126 ,  H04N19/13 ,  H04N19/136 ,  H04N19/137 ,  H04N19/14 ,  H04N19/147 ,  H04N19/174 ,  H04N19/176 ,  H04N19/196 ,  H04N19/42 ,  H04N19/423 ,  H04N19/46 ,  H04N19/503 ,  H04N19/567 ,  H04N19/57 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/85 ,  H04N19/87 ,  H04N19/91 ,  G06K9/00

CPC分类号： H04N19/42 ,  H04N19/61 ,  H04N5/145

摘要： Video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 are coupled with frame memory 10 through buffer and frame memory controlling portion 9 and controlling processor 1 through host interface portion 2. Frame memory 10 is accessed by video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 in time sharing manner. Controlling of video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 is centralized in controlling processor 1. Portions in dotted frame 20 are integrated in one LSI chip.

摘要翻译： 视频输入部分3，视频输出部分8，运动估计部分4，像素级运算部分5，可变长度编码部分6和代码输出部分7通过缓冲器和帧与帧存储器10耦合 存储器控制部分9和控制处理器1通过主机接口部分2.帧存储器10由视频输入部分3，视频输出部分8，运动估计部分4，像素级算术部分5，可变长度 - 编码部分6和代码输出部分7。 视频输入部分3，视频输出部分8，运动估计部分4，像素级算术部分5，可变长度编码部分6和代码输出部分7的控制集中在控制处理器1中。部分 点阵框架20集成在一个LSI芯片中。

公开(公告)号：US5589885A

公开(公告)日：1996-12-31

申请号：US400499

申请日：1995-03-08

申请人： Yasushi Ooi

发明人： Yasushi Ooi

IPC分类号： H04N19/50 ,  G06T9/00 ,  H04N19/42 ,  H04N19/423 ,  H04N19/503 ,  H04N19/51 ,  H04N19/577 ,  H04N19/61 ,  H04N19/625 ,  H04N19/85 ,  H04N19/91 ,  H04N19/93 ,  H04N7/32

CPC分类号： H04N19/42 ,  H04N19/61

摘要： A moving picture coding and decoding circuit which can cope with a plurality of algorithms to reduce the number of components and facilitate extension. A picture to be coded is inputted to a motion detection/prediction section, which outputs a predictive difference signal and a predictive signal. DCT processing and quantization are performed for the predictive difference signal by a conversion coding and decoding section, from which a conversion coefficient signal is outputted to an interface bus. The conversion coding and decoding section also executes dequantization and inverse DCT processing of the conversion coefficient, adds the predictive signal to the conversion coefficient and outputs a result of the picture coding to an image data bus. A programmable architecture as in a digital signal processor is applied to the conversion coding and decoding section. The conversion coefficient outputted from the conversion coding and decoding section is stored into a FIFO memory of a zigzag scan/entropy coding section and then undergoes coding in an entropy coding section. A bit stream thus coded is stored once into and then outputted as codes from another FIFO memory.

摘要翻译： 一种运动图像编码和解码电路，可以应对多种算法，以减少部件的数量并促进扩展。 要编码的图像被输入到运动检测/预测部分，其输出预测差分信号和预测信号。 通过转换编码和解码部分对预测差分信号进行DCT处理和量化，转换系数信号从该转换编码和解码部分输出到接口总线。 转换编码和解码部分还执行转换系数的逆量化和逆DCT处理，将预测信号与转换系数相加，并将图像编码的结果输出到图像数据总线。 在数字信号处理器中的可编程架构被应用于转换编码和解码部分。 从转换编码解码部输出的转换系数存储在Z字形扫描/熵编码部的FIFO存储器中，然后在熵编码部中进行编码。 这样编码的比特流被存储一次，然后作为来自另一个FIFO存储器的代码被输出。

公开(公告)号：US5553257A

公开(公告)日：1996-09-03

申请号：US189680

申请日：1994-02-01

申请人： Hideo Ishida ,  Yasushi Ooi

发明人： Hideo Ishida ,  Yasushi Ooi

IPC分类号： H03M7/42 ,  H04N7/26 ,  H04N7/30 ,  G06F12/00

CPC分类号： H03M7/42 ,  H04N19/13 ,  H04N19/60 ,  H04N19/91

摘要： An address generating circuit having a two-dimensional coding table which has respective coded words corresponding to a combination of x and y where the value of event A is determined as x and the value of event B as y (x and y are positive integers) between two events A and B, and stores the coded words in an address corresponding to each combination of x and y; coincidence detectors which input the values x and y of the events A and B and detect whether these values coincide with the integer of 1 to S (S is the maximum number among the integers satisfying S+log.sub.2 S

摘要翻译： 具有二维编码表的地址生成电路，其具有对应于事件A的值被确定为x的事件A的值和事件B的值对应于x和y的组合的各个编码字，y（x和y是正整数） 在两个事件A和B之间，并且将编码的字存储在与x和y的每个组合相对应的地址中; 输入事件A和B的值x和y并检测这些值是否与1到S的整数一致的符合检测器（S是满足S + log2S